marvell/axp/ddr3_spd.c

184 static u32 ddr3_get_max_val(u32 spd_val, u32 dimm_num, u32 static_val);
185 static u32 ddr3_get_min_val(u32 spd_val, u32 dimm_num, u32 static_val);
580 	u32 stat_val, spd_val;  local
789 	spd_val = ddr3_div(sum_info.min_active_to_precharge,
793 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
799 	spd_val = ddr3_div(sum_info.min_ras_to_cas_delay, ddr_clk_time, 1);
802 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
807 	spd_val = ddr3_div(sum_info.min_row_precharge_time, ddr_clk_time, 1);
810 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
815 	spd_val = ddr3_div(sum_info.min_write_recovery_time, ddr_clk_time, 1);
818 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
823 	spd_val = ddr3_div(sum_info.min_write_to_read_cmd_delay, ddr_clk_time, 1);
826 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
831 	spd_val = ddr3_div(sum_info.min_row_active_to_row_active, ddr_clk_time, 1);
834 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
839 	spd_val = ddr3_div(sum_info.min_read_to_prech_cmd_delay, ddr_clk_time, 1);
842 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
856 	spd_val = ddr3_div(sum_info.min_refresh_recovery, ddr_clk_time, 1);
859 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
871 	spd_val = ddr3_div(tmp, ddr_clk_time, 0);
874 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
880 	spd_val = ddr3_div(tmp, ddr_clk_time, 0);
883 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
1262 u32 ddr3_get_max_val(u32 spd_val, u32 dimm_num, u32 static_val)  argument
1266 		if (spd_val >= static_val)
1267 			return spd_val;
1274 	return spd_val;
1285 u32 ddr3_get_min_val(u32 spd_val, u32 dimm_num, u32 static_val)  argument
1289 		if (spd_val <= static_val)
1290 			return spd_val;
1296 	return spd_val;