189 extern u8 spd_data[SPD_SIZE];
248 		memset(spd_data, 0, SPD_SIZE * sizeof(u8));  in ddr3_spd_init()
250 		ret = i2c_read(dimm_addr, 0, 1, (uchar *)spd_data, SPD_SIZE);  in ddr3_spd_init()
256 	if (spd_data[SPD_DEV_TYPE_BYTE] != SPD_MEM_TYPE_DDR3)  in ddr3_spd_init()
264 	if ((spd_data[SPD_BUS_WIDTH_BYTE] & 0x18) >> 3)  in ddr3_spd_init()
268 	switch (spd_data[SPD_MODULE_TYPE_BYTE]) {  in ddr3_spd_init()
279 		info->type_info = (spd_data[SPD_MODULE_TYPE_BYTE]);  in ddr3_spd_init()
287 		(spd_data[SPD_ROW_NUM_BYTE] & SPD_ROW_NUM_MASK) >>  in ddr3_spd_init()
294 		(spd_data[SPD_COL_NUM_BYTE] & SPD_COL_NUM_MASK) >>  in ddr3_spd_init()
301 		(spd_data[SPD_MODULE_ORG_BYTE] & SPD_MODULE_BANK_NUM_MASK) >>  in ddr3_spd_init()
309 		1 << (3 + (spd_data[SPD_BUS_WIDTH_BYTE] & SPD_BUS_WIDTH_MASK));  in ddr3_spd_init()
314 		1 << (3 + ((spd_data[SPD_DEV_DENSITY_BYTE] >> 4) & 0x7));  in ddr3_spd_init()
320 		spd_data[SPD_DEV_DENSITY_BYTE] & SPD_DEV_DENSITY_MASK;  in ddr3_spd_init()
323 	info->sdram_width = 1 << (2 + (spd_data[SPD_MODULE_ORG_BYTE] &  in ddr3_spd_init()
354 		spd_data[SPD_ADDR_MAP_BYTE] & (1 << SPD_ADDR_MAP_MIRROR_OFFS);  in ddr3_spd_init()
358 	time_base = (1000 * spd_data[SPD_MTB_DIVIDEND_BYTE]) /  in ddr3_spd_init()
359 		spd_data[SPD_MTB_DIVISOR_BYTE];  in ddr3_spd_init()
362 	info->min_cycle_time = spd_data[SPD_TCK_BYTE] * time_base;  in ddr3_spd_init()
389 		(spd_data[SPD_SUP_CAS_LAT_MSB_BYTE] << 8) |  in ddr3_spd_init()
390 		spd_data[SPD_SUP_CAS_LAT_LSB_BYTE];  in ddr3_spd_init()
395 	info->min_cas_lat_time = (spd_data[SPD_TAA_BYTE] * time_base);  in ddr3_spd_init()
405 	info->min_write_recovery_time = spd_data[SPD_TWR_BYTE] * time_base;  in ddr3_spd_init()
410 	info->min_ras_to_cas_delay = spd_data[SPD_TRCD_BYTE] * time_base;  in ddr3_spd_init()
416 	    spd_data[SPD_TRRD_BYTE] * time_base;  in ddr3_spd_init()
421 	info->min_row_precharge_time = spd_data[SPD_TRP_BYTE] * time_base;  in ddr3_spd_init()
427 		(spd_data[SPD_TRAS_MSB_BYTE] & SPD_TRAS_MSB_MASK) << 8;  in ddr3_spd_init()
428 	info->min_active_to_precharge |= spd_data[SPD_TRAS_LSB_BYTE];  in ddr3_spd_init()
434 	info->min_refresh_recovery = spd_data[SPD_TRFC_MSB_BYTE] << 8;  in ddr3_spd_init()
435 	info->min_refresh_recovery |= spd_data[SPD_TRFC_LSB_BYTE];  in ddr3_spd_init()
444 	info->min_write_to_read_cmd_delay = spd_data[SPD_TWTR_BYTE] * time_base;  in ddr3_spd_init()
452 	info->min_read_to_prech_cmd_delay = spd_data[SPD_TRTP_BYTE] * time_base;  in ddr3_spd_init()
460 	tmp = ((spd_data[SPD_TFAW_MSB_BYTE] & SPD_TFAW_MSB_MASK) << 8) |  in ddr3_spd_init()
461 		spd_data[SPD_TFAW_LSB_BYTE];  in ddr3_spd_init()
470 			tmp = spd_data[SPD_RDIMM_RC_BYTE + rc / 2];  in ddr3_spd_init()
472 				spd_data[SPD_RDIMM_RC_BYTE + rc / 2] &  in ddr3_spd_init()
475 				(spd_data[SPD_RDIMM_RC_BYTE + rc / 2] >> 4) &  in ddr3_spd_init()
479 		vendor_low = spd_data[66];  in ddr3_spd_init()
480 		vendor_high = spd_data[65];  in ddr3_spd_init()