Lines Matching refs:rl_val
111 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
116 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
122 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
140 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
143 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
271 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw()
273 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw()
290 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
291 delay = dram_info->rl_val[cs][pup][D]; in ddr3_read_leveling_sw()
347 if (info->rl_val[cs][idx][S] == RL_UNLOCK_STATE) { in overrun()
350 if (info->rl_val[cs][idx][C] < RL_RETRY_COUNT) { in overrun()
353 info->rl_val[cs][idx][C]++; in overrun()
356 if (info->rl_val[cs][idx][C] == RL_RETRY_COUNT) { in overrun()
357 info->rl_val[cs][idx][C] = 0; in overrun()
358 info->rl_val[cs][idx][DS] = delay; in overrun()
359 info->rl_val[cs][idx][PS] = phase; in overrun()
362 info->rl_val[cs][idx][S] = RL_FINAL_STATE; in overrun()
422 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_rl_mode()
578 if (dram_info->rl_val[cs][idx][S] in ddr3_read_leveling_single_cs_rl_mode()
607 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
680 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_rl_mode()
681 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_rl_mode()
689 if (dram_info->rl_val[cs][pup][PS] < phase_min) in ddr3_read_leveling_single_cs_rl_mode()
690 phase_min = dram_info->rl_val[cs][pup][PS]; in ddr3_read_leveling_single_cs_rl_mode()
732 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_rl_mode()
776 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_window_mode()
833 if (dram_info->rl_val[cs][idx][S] == RL_WINDOW_STATE) { in ddr3_read_leveling_single_cs_window_mode()
846 dram_info->rl_val[cs][idx][DE] = delay; in ddr3_read_leveling_single_cs_window_mode()
847 dram_info->rl_val[cs][idx][PE] = phase; in ddr3_read_leveling_single_cs_window_mode()
849 dram_info->rl_val[cs][idx][S]++; in ddr3_read_leveling_single_cs_window_mode()
856 } else if (dram_info->rl_val[cs][idx][S] == in ddr3_read_leveling_single_cs_window_mode()
863 if (dram_info->rl_val[cs][idx][C] < in ddr3_read_leveling_single_cs_window_mode()
869 dram_info->rl_val[cs][idx][C]++; in ddr3_read_leveling_single_cs_window_mode()
872 if (dram_info->rl_val[cs][idx][C] == in ddr3_read_leveling_single_cs_window_mode()
874 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
875 dram_info->rl_val[cs][idx][DS] = in ddr3_read_leveling_single_cs_window_mode()
877 dram_info->rl_val[cs][idx][PS] = in ddr3_read_leveling_single_cs_window_mode()
879 dram_info->rl_val[cs][idx][S]++; /* Go to Window State */ in ddr3_read_leveling_single_cs_window_mode()
1083 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_window_mode()
1084 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
1095 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PS], 1); in ddr3_read_leveling_single_cs_window_mode()
1097 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DS], 2); in ddr3_read_leveling_single_cs_window_mode()
1099 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PE], 1); in ddr3_read_leveling_single_cs_window_mode()
1101 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DE], 2); in ddr3_read_leveling_single_cs_window_mode()
1110 if (dram_info->rl_val[cs][idx][PS] == 4) in ddr3_read_leveling_single_cs_window_mode()
1111 dram_info->rl_val[cs][idx][PS] = 1; in ddr3_read_leveling_single_cs_window_mode()
1112 if (dram_info->rl_val[cs][idx][PE] == 4) in ddr3_read_leveling_single_cs_window_mode()
1113 dram_info->rl_val[cs][idx][PE] = 1; in ddr3_read_leveling_single_cs_window_mode()
1115 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1116 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1117 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1118 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1128 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1129 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY_INV; in ddr3_read_leveling_single_cs_window_mode()
1132 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1133 MAX_DELAY + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1134 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1135 MAX_DELAY + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1143 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1144 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1148 if (dram_info->rl_val[cs][idx][PS] > 1) in ddr3_read_leveling_single_cs_window_mode()
1149 dram_info->rl_val[cs][idx][PS] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1150 if (dram_info->rl_val[cs][idx][PE] > 1) in ddr3_read_leveling_single_cs_window_mode()
1151 dram_info->rl_val[cs][idx][PE] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1154 delay_s = dram_info->rl_val[cs][idx][PS] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1155 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1156 delay_e = dram_info->rl_val[cs][idx][PE] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1157 dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1167 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1168 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1207 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_window_mode()