Lines Matching refs:pup
91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
99 for (pup = 0; in ddr3_read_leveling_hw()
100 pup < dram_info->num_of_total_pups; in ddr3_read_leveling_hw()
101 pup++) { in ddr3_read_leveling_hw()
102 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
104 pup = ECC_PUP; in ddr3_read_leveling_hw()
107 pup); in ddr3_read_leveling_hw()
111 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
116 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
121 cs, pup); in ddr3_read_leveling_hw()
122 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
130 for (pup = 0; in ddr3_read_leveling_hw()
131 pup < (dram_info->num_of_total_pups); in ddr3_read_leveling_hw()
132 pup++) { in ddr3_read_leveling_hw()
133 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
135 pup = ECC_PUP; in ddr3_read_leveling_hw()
137 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw()
140 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
143 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
181 u32 reg, cs, ecc, pup_num, phase, delay, pup; in ddr3_read_leveling_sw() local
265 for (pup = 0; in ddr3_read_leveling_sw()
266 pup < (dram_info->num_of_std_pups + dram_info->ecc_ena); in ddr3_read_leveling_sw()
267 pup++) { in ddr3_read_leveling_sw()
269 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw()
271 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw()
273 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw()
283 for (pup = 0; in ddr3_read_leveling_sw()
284 pup < (dram_info->num_of_std_pups + dram_info->ecc_ena); in ddr3_read_leveling_sw()
285 pup++) { in ddr3_read_leveling_sw()
287 pup_num = (pup == dram_info->num_of_std_pups) ? ECC_BIT : pup; in ddr3_read_leveling_sw()
290 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
291 delay = dram_info->rl_val[cs][pup][D]; in ddr3_read_leveling_sw()
335 static void overrun(u32 cs, MV_DRAM_INFO *info, u32 pup, u32 locked_pups, in overrun() argument
341 if (((~locked_pups >> pup) & 0x1) && (final_delay == 0)) { in overrun()
344 idx = pup + ecc * ECC_BIT; in overrun()
352 (u32)pup, 1); in overrun()
365 (u32)pup, 1); in overrun()
372 (u32)pup, 1); in overrun()
403 u32 reg, delay, phase, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_rl_mode() local
420 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_rl_mode()
421 pup++) in ddr3_read_leveling_single_cs_rl_mode()
422 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_rl_mode()
466 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
469 (REG_DRAM_TRAINING_2_OVERRUN_OFFS + pup)) & 0x1)) { in ddr3_read_leveling_single_cs_rl_mode()
470 overrun(cs, dram_info, pup, locked_pups, in ddr3_read_leveling_single_cs_rl_mode()
476 (u32)pup, 1); in ddr3_read_leveling_single_cs_rl_mode()
514 idx = pup + ecc * ECC_BIT; in ddr3_read_leveling_single_cs_rl_mode()
576 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
581 pup, 1); in ddr3_read_leveling_single_cs_rl_mode()
604 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
609 pup, 1); in ddr3_read_leveling_single_cs_rl_mode()
677 for (pup = 0; pup < in ddr3_read_leveling_single_cs_rl_mode()
679 pup++) { in ddr3_read_leveling_single_cs_rl_mode()
688 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
689 if (dram_info->rl_val[cs][pup][PS] < phase_min) in ddr3_read_leveling_single_cs_rl_mode()
690 phase_min = dram_info->rl_val[cs][pup][PS]; in ddr3_read_leveling_single_cs_rl_mode()
730 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_rl_mode()
731 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_rl_mode()
732 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_rl_mode()
755 u32 reg, delay, phase, sum, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_window_mode() local
774 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
775 pup++) in ddr3_read_leveling_single_cs_window_mode()
776 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_window_mode()
819 for (pup = 0; pup < (dram_info->num_of_std_pups * in ddr3_read_leveling_single_cs_window_mode()
820 (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_window_mode()
824 idx = pup + ecc * ECC_BIT; in ddr3_read_leveling_single_cs_window_mode()
829 pup)) & 0x1)) { in ddr3_read_leveling_single_cs_window_mode()
838 if (((~locked_pups >> pup) & 0x1) in ddr3_read_leveling_single_cs_window_mode()
842 (u32)pup, 1); in ddr3_read_leveling_single_cs_window_mode()
852 (u32)pup, 1); in ddr3_read_leveling_single_cs_window_mode()
865 if (((~locked_pups >> pup) & 0x1)) { in ddr3_read_leveling_single_cs_window_mode()
868 (u32)pup, 1); in ddr3_read_leveling_single_cs_window_mode()
886 (u32)pup, 1); in ddr3_read_leveling_single_cs_window_mode()
903 (u32)pup, 1); in ddr3_read_leveling_single_cs_window_mode()
1079 for (pup = 0; in ddr3_read_leveling_single_cs_window_mode()
1080 pup < in ddr3_read_leveling_single_cs_window_mode()
1082 pup++) { in ddr3_read_leveling_single_cs_window_mode()
1091 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_window_mode()
1093 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode()
1095 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PS], 1); in ddr3_read_leveling_single_cs_window_mode()
1097 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DS], 2); in ddr3_read_leveling_single_cs_window_mode()
1099 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PE], 1); in ddr3_read_leveling_single_cs_window_mode()
1101 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DE], 2); in ddr3_read_leveling_single_cs_window_mode()
1106 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
1107 pup++) { in ddr3_read_leveling_single_cs_window_mode()
1205 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_window_mode()
1206 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_window_mode()
1207 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_window_mode()