Lines Matching +full:single +full:- +full:phase
1 // SPDX-License-Identifier: GPL-2.0
55 * Desc: Execute the Read leveling phase by HW
56 * Args: dram_info - main struct
57 * freq - current sequence frequency
65 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw()
66 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
76 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
93 dram_info->rl_max_phase = 0; in ddr3_read_leveling_hw()
94 dram_info->rl_min_phase = 10; in ddr3_read_leveling_hw()
98 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
100 pup < dram_info->num_of_total_pups; in ddr3_read_leveling_hw()
102 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
103 && dram_info->ecc_ena) in ddr3_read_leveling_hw()
108 phase = (reg >> REG_PHY_PHASE_OFFS) & in ddr3_read_leveling_hw()
111 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
112 if (phase > dram_info->rl_max_phase) in ddr3_read_leveling_hw()
113 dram_info->rl_max_phase = phase; in ddr3_read_leveling_hw()
114 if (phase < dram_info->rl_min_phase) in ddr3_read_leveling_hw()
115 dram_info->rl_min_phase = phase; in ddr3_read_leveling_hw()
116 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
122 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
127 DEBUG_RL_C("DDR3 - Read Leveling - Results for CS - ", in ddr3_read_leveling_hw()
131 pup < (dram_info->num_of_total_pups); in ddr3_read_leveling_hw()
133 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
134 && dram_info->ecc_ena) in ddr3_read_leveling_hw()
136 DEBUG_RL_S("DDR3 - Read Leveling - PUP: "); in ddr3_read_leveling_hw()
138 DEBUG_RL_S(", Phase: "); in ddr3_read_leveling_hw()
139 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw()
142 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw()
150 dram_info->rd_rdy_dly = in ddr3_read_leveling_hw()
153 dram_info->rd_smpl_dly = in ddr3_read_leveling_hw()
157 DEBUG_RL_C("DDR3 - Read Leveling - Read Sample Delay: ", in ddr3_read_leveling_hw()
158 dram_info->rd_smpl_dly, 2); in ddr3_read_leveling_hw()
159 DEBUG_RL_C("DDR3 - Read Leveling - Read Ready Delay: ", in ddr3_read_leveling_hw()
160 dram_info->rd_rdy_dly, 2); in ddr3_read_leveling_hw()
161 DEBUG_RL_S("DDR3 - Read Leveling - HW RL Ended Successfully\n"); in ddr3_read_leveling_hw()
166 DEBUG_RL_S("DDR3 - Read Leveling - HW RL Error\n"); in ddr3_read_leveling_hw()
173 * Desc: Execute the Read leveling phase by SW
174 * Args: dram_info - main struct
175 * freq - current sequence frequency
181 u32 reg, cs, ecc, pup_num, phase, delay, pup; in ddr3_read_leveling_sw() local
184 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_sw()
185 DEBUG_RL_S("DDR3 - Read Leveling - Starting SW RL procedure\n"); in ddr3_read_leveling_sw()
191 /* [0]=1 - Enable SW override */ in ddr3_read_leveling_sw()
192 /* 0x15B8 - Training SW 2 Register */ in ddr3_read_leveling_sw()
196 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_read_leveling_sw()
198 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_sw()
202 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_sw()
203 DEBUG_RL_C("DDR3 - Read Leveling - CS - ", (u32) cs, 1); in ddr3_read_leveling_sw()
205 for (ecc = 0; ecc <= (dram_info->ecc_ena); ecc++) { in ddr3_read_leveling_sw()
206 /* ECC Support - Switch ECC Mux on ecc=1 */ in ddr3_read_leveling_sw()
209 reg |= (dram_info->ecc_ena * in ddr3_read_leveling_sw()
214 DEBUG_RL_S("DDR3 - Read Leveling - ECC Mux Enabled\n"); in ddr3_read_leveling_sw()
216 DEBUG_RL_S("DDR3 - Read Leveling - ECC Mux Disabled\n"); in ddr3_read_leveling_sw()
222 reg |= (dram_info->cl << in ddr3_read_leveling_sw()
232 reg |= ((dram_info->cl + 1) << in ddr3_read_leveling_sw()
236 reg |= ((dram_info->cl + 2) << in ddr3_read_leveling_sw()
241 /* Read leveling Single CS[cs] */ in ddr3_read_leveling_sw()
262 DEBUG_RL_C("DDR3 - Read Leveling - Results for CS - ", (u32) cs, in ddr3_read_leveling_sw()
266 pup < (dram_info->num_of_std_pups + dram_info->ecc_ena); in ddr3_read_leveling_sw()
268 DEBUG_RL_S("DDR3 - Read Leveling - PUP: "); in ddr3_read_leveling_sw()
270 DEBUG_RL_S(", Phase: "); in ddr3_read_leveling_sw()
271 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw()
273 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw()
277 DEBUG_RL_C("DDR3 - Read Leveling - Read Sample Delay: ", in ddr3_read_leveling_sw()
278 dram_info->rd_smpl_dly, 2); in ddr3_read_leveling_sw()
279 DEBUG_RL_C("DDR3 - Read Leveling - Read Ready Delay: ", in ddr3_read_leveling_sw()
280 dram_info->rd_rdy_dly, 2); in ddr3_read_leveling_sw()
284 pup < (dram_info->num_of_std_pups + dram_info->ecc_ena); in ddr3_read_leveling_sw()
286 /* ECC support - bit 8 */ in ddr3_read_leveling_sw()
287 pup_num = (pup == dram_info->num_of_std_pups) ? ECC_BIT : pup; in ddr3_read_leveling_sw()
290 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
291 delay = dram_info->rl_val[cs][pup][D]; in ddr3_read_leveling_sw()
292 ddr3_write_pup_reg(PUP_RL_MODE, cs, pup_num, phase, in ddr3_read_leveling_sw()
300 /* 0x15B8 - Training SW 2 Register */ in ddr3_read_leveling_sw()
308 /* ECC Support - Switch ECC Mux off ecc=0 */ in ddr3_read_leveling_sw()
314 reg_write(REG_DRAM_TRAINING_ADDR, 0); /* 0x15B0 - Training Register */ in ddr3_read_leveling_sw()
320 /* [0] = 0 - Disable SW override */ in ddr3_read_leveling_sw()
322 /* [3] = 1 - Disable RL MODE */ in ddr3_read_leveling_sw()
323 /* 0x15B8 - Training SW 2 Register */ in ddr3_read_leveling_sw()
326 DEBUG_RL_S("DDR3 - Read Leveling - Finished RL procedure for all CS\n"); in ddr3_read_leveling_sw()
338 u32 phase) in overrun() argument
347 if (info->rl_val[cs][idx][S] == RL_UNLOCK_STATE) { in overrun()
349 /* Match expected value ? - Update State Machine */ in overrun()
350 if (info->rl_val[cs][idx][C] < RL_RETRY_COUNT) { in overrun()
351 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We have no overrun and a match on pup: ", in overrun()
353 info->rl_val[cs][idx][C]++; in overrun()
355 /* If pup got to last state - lock the delays */ in overrun()
356 if (info->rl_val[cs][idx][C] == RL_RETRY_COUNT) { in overrun()
357 info->rl_val[cs][idx][C] = 0; in overrun()
358 info->rl_val[cs][idx][DS] = delay; in overrun()
359 info->rl_val[cs][idx][PS] = phase; in overrun()
362 info->rl_val[cs][idx][S] = RL_FINAL_STATE; in overrun()
364 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We have locked pup: ", in overrun()
368 * If first lock - need to lock delays in overrun()
371 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We got first lock on pup: ", in overrun()
378 * there was match - dont increment in overrun()
391 * Desc: Execute Read leveling for single Chip select
392 * Args: cs - current chip select
393 * freq - current sequence frequency
394 * ecc - ecc iteration indication
395 * dram_info - main struct
403 u32 reg, delay, phase, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_rl_mode() local
409 DEBUG_RL_FULL_C("DDR3 - Read Leveling - Single CS - ", (u32) cs, 1); in ddr3_read_leveling_single_cs_rl_mode()
412 phase = 0; in ddr3_read_leveling_single_cs_rl_mode()
414 rd_sample_delay = dram_info->cl; in ddr3_read_leveling_single_cs_rl_mode()
420 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_rl_mode()
422 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_rl_mode()
428 DEBUG_RL_FULL_S("DDR3 - Read Leveling - RdSmplDly = "); in ddr3_read_leveling_single_cs_rl_mode()
431 DEBUG_RL_FULL_D(dram_info->rd_rdy_dly, 2); in ddr3_read_leveling_single_cs_rl_mode()
432 DEBUG_RL_FULL_S(", Phase = "); in ddr3_read_leveling_single_cs_rl_mode()
433 DEBUG_RL_FULL_D(phase, 1); in ddr3_read_leveling_single_cs_rl_mode()
439 * Broadcast to all PUPs current RL delays: DQS phase, in ddr3_read_leveling_single_cs_rl_mode()
442 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_rl_mode()
447 /* 0x15B8 - Training SW 2 Register */ in ddr3_read_leveling_single_cs_rl_mode()
466 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
473 delay, phase); in ddr3_read_leveling_single_cs_rl_mode()
475 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We got overrun on pup: ", in ddr3_read_leveling_single_cs_rl_mode()
480 if (locked_sum == (dram_info->num_of_std_pups * in ddr3_read_leveling_single_cs_rl_mode()
481 (1 - ecc) + ecc)) { in ddr3_read_leveling_single_cs_rl_mode()
483 DEBUG_RL_FULL_S("DDR3 - Read Leveling - Single Cs - All pups locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
499 DEBUG_RL_FULL_S("DDR3 - Read Leveling - Counter is >=1 and <3\n"); in ddr3_read_leveling_single_cs_rl_mode()
500 …DEBUG_RL_FULL_S("DDR3 - Read Leveling - So we will not increment the delay to see if locked again\… in ddr3_read_leveling_single_cs_rl_mode()
502 …DEBUG_RL_FULL_S("DDR3 - Read Leveling - repeat_max_cnt reached max so now we will increment the de… in ddr3_read_leveling_single_cs_rl_mode()
518 if ((!ratio_2to1) && ((phase == 0) || (phase == 4))) in ddr3_read_leveling_single_cs_rl_mode()
531 if ((!ratio_2to1 && phase == in ddr3_read_leveling_single_cs_rl_mode()
533 || (ratio_2to1 && phase == in ddr3_read_leveling_single_cs_rl_mode()
538 /* Phase+CL Incrementation */ in ddr3_read_leveling_single_cs_rl_mode()
545 if (phase < MAX_PHASE_RL_L_1TO1) { in ddr3_read_leveling_single_cs_rl_mode()
546 if (phase == 1) { in ddr3_read_leveling_single_cs_rl_mode()
547 phase = 4; in ddr3_read_leveling_single_cs_rl_mode()
549 phase++; in ddr3_read_leveling_single_cs_rl_mode()
553 DEBUG_RL_FULL_S("DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
554 DEBUG_RL_S("1)DDR3 - Read Leveling - ERROR - NOT all PUPs Locked n"); in ddr3_read_leveling_single_cs_rl_mode()
559 if (phase < MAX_PHASE_RL_UL_1TO1) { in ddr3_read_leveling_single_cs_rl_mode()
560 phase++; in ddr3_read_leveling_single_cs_rl_mode()
564 phase = 0; in ddr3_read_leveling_single_cs_rl_mode()
571 if (phase < MAX_PHASE_RL_L_2TO1) { in ddr3_read_leveling_single_cs_rl_mode()
572 phase++; in ddr3_read_leveling_single_cs_rl_mode()
574 DEBUG_RL_FULL_S("DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
575 DEBUG_RL_S("2)DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
576 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
578 if (dram_info->rl_val[cs][idx][S] in ddr3_read_leveling_single_cs_rl_mode()
588 if (phase < MAX_PHASE_RL_UL_2TO1) in ddr3_read_leveling_single_cs_rl_mode()
589 phase++; in ddr3_read_leveling_single_cs_rl_mode()
591 phase = 0; in ddr3_read_leveling_single_cs_rl_mode()
597 * phase = 0, need to increment rd_sample_dly in ddr3_read_leveling_single_cs_rl_mode()
599 if (phase == 0 && first_octet_locked == 0) { in ddr3_read_leveling_single_cs_rl_mode()
602 DEBUG_RL_FULL_S("DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
603 DEBUG_RL_S("3)DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
604 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
606 if (dram_info-> in ddr3_read_leveling_single_cs_rl_mode()
629 * hash table (Need to do this in every phase in ddr3_read_leveling_single_cs_rl_mode()
635 switch (phase) { in ddr3_read_leveling_single_cs_rl_mode()
661 (phase * in ddr3_read_leveling_single_cs_rl_mode()
672 dram_info->rd_smpl_dly = rd_sample_delay; in ddr3_read_leveling_single_cs_rl_mode()
673 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_rl_mode()
678 (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_rl_mode()
680 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_rl_mode()
681 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_rl_mode()
688 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
689 if (dram_info->rl_val[cs][pup][PS] < phase_min) in ddr3_read_leveling_single_cs_rl_mode()
690 phase_min = dram_info->rl_val[cs][pup][PS]; in ddr3_read_leveling_single_cs_rl_mode()
695 * do this in every phase change) in ddr3_read_leveling_single_cs_rl_mode()
727 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_rl_mode()
729 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_rl_mode()
730 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_rl_mode()
732 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_rl_mode()
743 * Desc: Execute Read leveling for single Chip select
744 * Args: cs - current chip select
745 * freq - current sequence frequency
746 * ecc - ecc iteration indication
747 * dram_info - main struct
755 u32 reg, delay, phase, sum, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_window_mode() local
761 DEBUG_RL_FULL_C("DDR3 - Read Leveling - Single CS - ", (u32) cs, 1); in ddr3_read_leveling_single_cs_window_mode()
764 phase = 0; in ddr3_read_leveling_single_cs_window_mode()
766 rd_sample_delay = dram_info->cl; in ddr3_read_leveling_single_cs_window_mode()
774 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
776 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_window_mode()
782 DEBUG_RL_FULL_S("DDR3 - Read Leveling - RdSmplDly = "); in ddr3_read_leveling_single_cs_window_mode()
785 DEBUG_RL_FULL_D(dram_info->rd_rdy_dly, 2); in ddr3_read_leveling_single_cs_window_mode()
786 DEBUG_RL_FULL_S(", Phase = "); in ddr3_read_leveling_single_cs_window_mode()
787 DEBUG_RL_FULL_D(phase, 1); in ddr3_read_leveling_single_cs_window_mode()
793 * Broadcast to all PUPs current RL delays: DQS phase,leveling in ddr3_read_leveling_single_cs_window_mode()
796 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_window_mode()
801 /* 0x15B8 - Training SW 2 Register */ in ddr3_read_leveling_single_cs_window_mode()
819 for (pup = 0; pup < (dram_info->num_of_std_pups * in ddr3_read_leveling_single_cs_window_mode()
820 (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_window_mode()
833 if (dram_info->rl_val[cs][idx][S] == RL_WINDOW_STATE) { in ddr3_read_leveling_single_cs_window_mode()
835 * Match expected value ? - Update in ddr3_read_leveling_single_cs_window_mode()
840 /* Match - Still inside the Window */ in ddr3_read_leveling_single_cs_window_mode()
841 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We got another match inside the window for pup: ", in ddr3_read_leveling_single_cs_window_mode()
845 /* We got fail -> this is the end of the window */ in ddr3_read_leveling_single_cs_window_mode()
846 dram_info->rl_val[cs][idx][DE] = delay; in ddr3_read_leveling_single_cs_window_mode()
847 dram_info->rl_val[cs][idx][PE] = phase; in ddr3_read_leveling_single_cs_window_mode()
849 dram_info->rl_val[cs][idx][S]++; in ddr3_read_leveling_single_cs_window_mode()
851 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We finished the window for pup: ", in ddr3_read_leveling_single_cs_window_mode()
856 } else if (dram_info->rl_val[cs][idx][S] == in ddr3_read_leveling_single_cs_window_mode()
860 * Match expected value ? - Update in ddr3_read_leveling_single_cs_window_mode()
863 if (dram_info->rl_val[cs][idx][C] < in ddr3_read_leveling_single_cs_window_mode()
867 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We have no overrun and a match on pup: ", in ddr3_read_leveling_single_cs_window_mode()
869 dram_info->rl_val[cs][idx][C]++; in ddr3_read_leveling_single_cs_window_mode()
871 /* If pup got to last state - lock the delays */ in ddr3_read_leveling_single_cs_window_mode()
872 if (dram_info->rl_val[cs][idx][C] == in ddr3_read_leveling_single_cs_window_mode()
874 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
875 dram_info->rl_val[cs][idx][DS] = in ddr3_read_leveling_single_cs_window_mode()
877 dram_info->rl_val[cs][idx][PS] = in ddr3_read_leveling_single_cs_window_mode()
878 phase; in ddr3_read_leveling_single_cs_window_mode()
879 dram_info->rl_val[cs][idx][S]++; /* Go to Window State */ in ddr3_read_leveling_single_cs_window_mode()
883 /* IF First lock - need to lock delays */ in ddr3_read_leveling_single_cs_window_mode()
885 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We got first lock on pup: ", in ddr3_read_leveling_single_cs_window_mode()
893 /* if pup is in not in final state but there was match - dont increment counter */ in ddr3_read_leveling_single_cs_window_mode()
902 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We got overrun on pup: ", in ddr3_read_leveling_single_cs_window_mode()
908 if (final_sum == (dram_info->num_of_std_pups * (1 - ecc) + ecc)) { in ddr3_read_leveling_single_cs_window_mode()
910 DEBUG_RL_FULL_S("DDR3 - Read Leveling - Single Cs - All pups locked\n"); in ddr3_read_leveling_single_cs_window_mode()
926 DEBUG_RL_FULL_S("DDR3 - Read Leveling - Counter is >=1 and <3\n"); in ddr3_read_leveling_single_cs_window_mode()
927 …DEBUG_RL_FULL_S("DDR3 - Read Leveling - So we will not increment the delay to see if locked again\… in ddr3_read_leveling_single_cs_window_mode()
929 …DEBUG_RL_FULL_S("DDR3 - Read Leveling - repeat_max_cnt reached max so now we will increment the de… in ddr3_read_leveling_single_cs_window_mode()
955 && phase == MAX_PHASE_RL_L_1TO1) in ddr3_read_leveling_single_cs_window_mode()
957 && phase == in ddr3_read_leveling_single_cs_window_mode()
962 /* Phase+CL Incrementation */ in ddr3_read_leveling_single_cs_window_mode()
968 if (phase < MAX_PHASE_RL_L_1TO1) { in ddr3_read_leveling_single_cs_window_mode()
970 if (phase == 0) in ddr3_read_leveling_single_cs_window_mode()
972 if (phase == 1) in ddr3_read_leveling_single_cs_window_mode()
974 phase = 4; in ddr3_read_leveling_single_cs_window_mode()
976 phase++; in ddr3_read_leveling_single_cs_window_mode()
978 DEBUG_RL_FULL_S("DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_window_mode()
983 if (phase < MAX_PHASE_RL_UL_1TO1) { in ddr3_read_leveling_single_cs_window_mode()
985 if (phase == 0) in ddr3_read_leveling_single_cs_window_mode()
986 phase = 4; in ddr3_read_leveling_single_cs_window_mode()
988 phase++; in ddr3_read_leveling_single_cs_window_mode()
991 phase = 0; in ddr3_read_leveling_single_cs_window_mode()
997 if (phase < MAX_PHASE_RL_L_2TO1) { in ddr3_read_leveling_single_cs_window_mode()
998 phase++; in ddr3_read_leveling_single_cs_window_mode()
1000 DEBUG_RL_FULL_S("DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_window_mode()
1005 if (phase < MAX_PHASE_RL_UL_2TO1) in ddr3_read_leveling_single_cs_window_mode()
1006 phase++; in ddr3_read_leveling_single_cs_window_mode()
1008 phase = 0; in ddr3_read_leveling_single_cs_window_mode()
1014 * now phase = 0, need to increment in ddr3_read_leveling_single_cs_window_mode()
1017 if (phase == 0 && first_octet_locked == 0) { in ddr3_read_leveling_single_cs_window_mode()
1034 * hash table (Need to do this in every phase in ddr3_read_leveling_single_cs_window_mode()
1040 switch (phase) { in ddr3_read_leveling_single_cs_window_mode()
1064 add = (add >> phase * in ddr3_read_leveling_single_cs_window_mode()
1074 dram_info->rd_smpl_dly = rd_sample_delay; in ddr3_read_leveling_single_cs_window_mode()
1075 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_window_mode()
1081 (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
1083 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_window_mode()
1084 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
1091 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_window_mode()
1092 DEBUG_RL_S("DDR3 - Read Leveling - Window info - PUP: "); in ddr3_read_leveling_single_cs_window_mode()
1095 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PS], 1); in ddr3_read_leveling_single_cs_window_mode()
1097 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DS], 2); in ddr3_read_leveling_single_cs_window_mode()
1099 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PE], 1); in ddr3_read_leveling_single_cs_window_mode()
1101 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DE], 2); in ddr3_read_leveling_single_cs_window_mode()
1106 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
1110 if (dram_info->rl_val[cs][idx][PS] == 4) in ddr3_read_leveling_single_cs_window_mode()
1111 dram_info->rl_val[cs][idx][PS] = 1; in ddr3_read_leveling_single_cs_window_mode()
1112 if (dram_info->rl_val[cs][idx][PE] == 4) in ddr3_read_leveling_single_cs_window_mode()
1113 dram_info->rl_val[cs][idx][PE] = 1; in ddr3_read_leveling_single_cs_window_mode()
1115 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1116 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1117 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1118 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1120 tmp = (delay_e - delay_s) / 2 + delay_s; in ddr3_read_leveling_single_cs_window_mode()
1121 phase = tmp / MAX_DELAY_INV; in ddr3_read_leveling_single_cs_window_mode()
1122 if (phase == 1) /* 1:1 mode */ in ddr3_read_leveling_single_cs_window_mode()
1123 phase = 4; in ddr3_read_leveling_single_cs_window_mode()
1125 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()
1126 phase_min = phase; in ddr3_read_leveling_single_cs_window_mode()
1128 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1129 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY_INV; in ddr3_read_leveling_single_cs_window_mode()
1132 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1133 MAX_DELAY + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1134 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1135 MAX_DELAY + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1137 tmp = (delay_e - delay_s) / 2 + delay_s; in ddr3_read_leveling_single_cs_window_mode()
1138 phase = tmp / MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1140 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()
1141 phase_min = phase; in ddr3_read_leveling_single_cs_window_mode()
1143 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1144 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1148 if (dram_info->rl_val[cs][idx][PS] > 1) in ddr3_read_leveling_single_cs_window_mode()
1149 dram_info->rl_val[cs][idx][PS] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1150 if (dram_info->rl_val[cs][idx][PE] > 1) in ddr3_read_leveling_single_cs_window_mode()
1151 dram_info->rl_val[cs][idx][PE] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1154 delay_s = dram_info->rl_val[cs][idx][PS] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1155 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1156 delay_e = dram_info->rl_val[cs][idx][PE] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1157 dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1159 tmp = (delay_e - delay_s) / 2 + delay_s; in ddr3_read_leveling_single_cs_window_mode()
1160 phase = tmp / MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1161 if (!ratio_2to1 && phase > 1) /* 1:1 mode */ in ddr3_read_leveling_single_cs_window_mode()
1162 phase += 2; in ddr3_read_leveling_single_cs_window_mode()
1164 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()
1165 phase_min = phase; in ddr3_read_leveling_single_cs_window_mode()
1167 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1168 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1172 /* Set current rdReadyDelay according to the hash table (Need to do this in every phase change) */ in ddr3_read_leveling_single_cs_window_mode()
1202 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_window_mode()
1204 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_window_mode()
1205 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_window_mode()
1207 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_window_mode()