Lines Matching full:delay
91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
110 delay = reg & PUP_DELAY_MASK; in ddr3_read_leveling_hw()
116 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
141 DEBUG_RL_S(", Delay: "); in ddr3_read_leveling_hw()
157 DEBUG_RL_C("DDR3 - Read Leveling - Read Sample Delay: ", in ddr3_read_leveling_hw()
159 DEBUG_RL_C("DDR3 - Read Leveling - Read Ready Delay: ", in ddr3_read_leveling_hw()
181 u32 reg, cs, ecc, pup_num, phase, delay, pup; in ddr3_read_leveling_sw() local
226 /* Set current Ready delay */ in ddr3_read_leveling_sw()
272 DEBUG_RL_S(", Delay: "); in ddr3_read_leveling_sw()
277 DEBUG_RL_C("DDR3 - Read Leveling - Read Sample Delay: ", in ddr3_read_leveling_sw()
279 DEBUG_RL_C("DDR3 - Read Leveling - Read Ready Delay: ", in ddr3_read_leveling_sw()
291 delay = dram_info->rl_val[cs][pup][D]; in ddr3_read_leveling_sw()
293 delay); in ddr3_read_leveling_sw()
337 int *counter_in_progress, int final_delay, u32 delay, in overrun() argument
358 info->rl_val[cs][idx][DS] = delay; in overrun()
403 u32 reg, delay, phase, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_rl_mode() local
413 delay = 0; in ddr3_read_leveling_single_cs_rl_mode()
434 DEBUG_RL_FULL_S(", Delay = "); in ddr3_read_leveling_single_cs_rl_mode()
435 DEBUG_RL_FULL_D(delay, 2); in ddr3_read_leveling_single_cs_rl_mode()
440 * leveling delay in ddr3_read_leveling_single_cs_rl_mode()
442 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_rl_mode()
473 delay, phase); in ddr3_read_leveling_single_cs_rl_mode()
500 …DEBUG_RL_FULL_S("DDR3 - Read Leveling - So we will not increment the delay to see if locked again\… in ddr3_read_leveling_single_cs_rl_mode()
502 …L_FULL_S("DDR3 - Read Leveling - repeat_max_cnt reached max so now we will increment the delay\n"); in ddr3_read_leveling_single_cs_rl_mode()
523 /* Increment Delay */ in ddr3_read_leveling_single_cs_rl_mode()
524 if (delay < ui_max_delay) { in ddr3_read_leveling_single_cs_rl_mode()
525 delay++; in ddr3_read_leveling_single_cs_rl_mode()
527 * Mark the last delay/pahse place for in ddr3_read_leveling_single_cs_rl_mode()
530 if (delay == ui_max_delay) { in ddr3_read_leveling_single_cs_rl_mode()
539 delay = 0; in ddr3_read_leveling_single_cs_rl_mode()
550 delay = MIN_DELAY_PHASE_1_LIMIT; in ddr3_read_leveling_single_cs_rl_mode()
561 delay = in ddr3_read_leveling_single_cs_rl_mode()
755 u32 reg, delay, phase, sum, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_window_mode() local
765 delay = 0; in ddr3_read_leveling_single_cs_window_mode()
788 DEBUG_RL_FULL_S(", Delay = "); in ddr3_read_leveling_single_cs_window_mode()
789 DEBUG_RL_FULL_D(delay, 2); in ddr3_read_leveling_single_cs_window_mode()
794 * delay in ddr3_read_leveling_single_cs_window_mode()
796 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_window_mode()
846 dram_info->rl_val[cs][idx][DE] = delay; in ddr3_read_leveling_single_cs_window_mode()
876 delay; in ddr3_read_leveling_single_cs_window_mode()
927 …DEBUG_RL_FULL_S("DDR3 - Read Leveling - So we will not increment the delay to see if locked again\… in ddr3_read_leveling_single_cs_window_mode()
929 …L_FULL_S("DDR3 - Read Leveling - repeat_max_cnt reached max so now we will increment the delay\n"); in ddr3_read_leveling_single_cs_window_mode()
945 /* Increment Delay */ in ddr3_read_leveling_single_cs_window_mode()
946 if (delay < ui_max_delay) { in ddr3_read_leveling_single_cs_window_mode()
947 /* Delay Incrementation */ in ddr3_read_leveling_single_cs_window_mode()
948 delay++; in ddr3_read_leveling_single_cs_window_mode()
949 if (delay == ui_max_delay) { in ddr3_read_leveling_single_cs_window_mode()
951 * Mark the last delay/pahse place in ddr3_read_leveling_single_cs_window_mode()
963 delay = 0; in ddr3_read_leveling_single_cs_window_mode()
1125 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()
1140 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()
1164 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()