Lines Matching full:dq
44 /* PBS locked dq (per pup) */
96 u32 pup, dq, pups, cur_max_pup, valid_pup, reg; in ddr3_pbs_tx() local
125 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_tx()
126 skew_sum_array[pup][dq] = 0; in ddr3_pbs_tx()
173 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
176 (max_pup - 1)][dq] = in ddr3_pbs_tx()
200 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
206 [dq], CS0, (1 - ecc) * in ddr3_pbs_tx()
212 * Shift DQ ADLL right, One step before in ddr3_pbs_tx()
253 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
254 /* Set skew value for all dq */ in ddr3_pbs_tx()
261 DEBUG_PBS_S("DQ"); in ddr3_pbs_tx()
262 DEBUG_PBS_D(dq, 1); in ddr3_pbs_tx()
266 dq], 2); in ddr3_pbs_tx()
277 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
279 [dq] += skew_array in ddr3_pbs_tx()
280 [((pup) * DQ_NUM) + dq]; in ddr3_pbs_tx()
302 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
303 /* set skew value for all dq */ in ddr3_pbs_tx()
305 DEBUG_PBS_S("DQ"); in ddr3_pbs_tx()
306 DEBUG_PBS_D(dq, 1); in ddr3_pbs_tx()
308 DEBUG_PBS_D(skew_sum_array[pup][dq] / in ddr3_pbs_tx()
328 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
329 pattern_skew_array[pup][dq] += in ddr3_pbs_tx()
330 (skew_sum_array[pup][dq] / in ddr3_pbs_tx()
338 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_tx()
339 skew_array[((pup) * DQ_NUM) + dq] = in ddr3_pbs_tx()
340 pattern_skew_array[pup][dq] / COUNT_PBS_PATTERN; in ddr3_pbs_tx()
353 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
354 /* Set skew value for all dq */ in ddr3_pbs_tx()
360 DEBUG_PBS_S("DQ"); in ddr3_pbs_tx()
361 DEBUG_PBS_D(dq, 1); in ddr3_pbs_tx()
363 DEBUG_PBS_D(skew_array[(pup * DQ_NUM) + dq], 2); in ddr3_pbs_tx()
397 * Desc: Execute the Tx shift DQ phase.
448 * Increment (Move to right - ADLL) DQ TX delay in ddr3_tx_shift_dqs_adll_step_before_fail()
480 * DQ TX delay for current failed pups and save in ddr3_tx_shift_dqs_adll_step_before_fail()
491 DEBUG_PBS_FULL_S("DDR3 - PBS Tx - Shift DQ - Adll value reached maximum\n"); in ddr3_tx_shift_dqs_adll_step_before_fail()
538 u32 pup, dq, pups, cur_max_pup, valid_pup, reg; in ddr3_pbs_rx() local
568 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_rx()
569 skew_sum_array[pup][dq] = 0; in ddr3_pbs_rx()
615 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_rx()
617 pup + ecc * (max_pup - 1)][dq] = in ddr3_pbs_rx()
640 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_rx()
646 [dq], CS0, in ddr3_pbs_rx()
710 for (dq = 0; in ddr3_pbs_rx()
711 dq < DQ_NUM; dq++) in ddr3_pbs_rx()
717 [dq], CS0, in ddr3_pbs_rx()
764 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_rx()
765 /* Set skew value for all dq */ in ddr3_pbs_rx()
772 DEBUG_PBS_FULL_S("DQ"); in ddr3_pbs_rx()
773 DEBUG_PBS_FULL_D(dq, 1); in ddr3_pbs_rx()
778 dq], 2); in ddr3_pbs_rx()
789 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_rx()
792 [dq] += in ddr3_pbs_rx()
793 skew_array[((pup) * DQ_NUM) + dq]; in ddr3_pbs_rx()
816 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_rx()
817 pattern_skew_array[pup][dq] += in ddr3_pbs_rx()
818 (skew_sum_array[pup][dq] / in ddr3_pbs_rx()
834 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_rx()
835 /* Set skew value for all dq */ in ddr3_pbs_rx()
841 DEBUG_PBS_S("DQ"); in ddr3_pbs_rx()
842 DEBUG_PBS_D(dq, 1); in ddr3_pbs_rx()
844 DEBUG_PBS_D(skew_sum_array[pup][dq] / in ddr3_pbs_rx()
854 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_rx()
855 skew_array[((pup) * DQ_NUM) + dq] = in ddr3_pbs_rx()
856 pattern_skew_array[pup][dq] / COUNT_PBS_PATTERN; in ddr3_pbs_rx()
869 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_rx()
870 /* Set skew value for all dq */ in ddr3_pbs_rx()
876 DEBUG_PBS_S("DQ"); in ddr3_pbs_rx()
877 DEBUG_PBS_D(dq, 1); in ddr3_pbs_rx()
879 DEBUG_PBS_D(skew_array[(pup * DQ_NUM) + dq], 2); in ddr3_pbs_rx()
909 * Desc: Execute the Rx shift DQ phase.
1089 u32 dq; in lock_pups() local
1100 for (dq = 0; dq < DQ_NUM; dq++) { in lock_pups()
1101 if (IS_PUP_ACTIVE(unlock_pup_dq_array[dq], pup) == 1) { in lock_pups()
1104 /* Lock current dq */ in lock_pups()
1105 unlock_pup_dq_array[dq] &= ~(1 << pup); in lock_pups()
1106 skew_array[(pup * DQ_NUM) + dq] = pbs_curr_val; in lock_pups()
1114 pbs_dq_mapping[idx][dq], CS0, in lock_pups()
1140 * Bit array to indicate if we already get fail on bit per pup & dq bit in ddr3_pbs_per_bit()
1148 u32 pup, dq; in ddr3_pbs_per_bit() local
1152 /* bit array that indicates all dq of the pup locked */ in ddr3_pbs_per_bit()
1167 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_per_bit()
1168 cmp_unlock_pup_dq_array[pbs_cmp_retry][dq] = *pcur_pup; in ddr3_pbs_per_bit()
1201 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_per_bit()
1202 /* Check DQ bits to see if locked in all pups */ in ddr3_pbs_per_bit()
1203 if (unlock_pup_dq_array[dq] == 0) { in ddr3_pbs_per_bit()
1204 DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - All pups are locked for DQ "); in ddr3_pbs_per_bit()
1205 DEBUG_PBS_FULL_D(dq, 1); in ddr3_pbs_per_bit()
1215 if (IS_PUP_ACTIVE(unlock_pup_dq_array[dq], pup) in ddr3_pbs_per_bit()
1221 PUP_PBS_TX + pbs_dq_mapping[idx][dq], in ddr3_pbs_per_bit()
1225 PUP_PBS_RX + pbs_dq_mapping[idx][dq], in ddr3_pbs_per_bit()
1249 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_per_bit()
1250 if ((IS_PUP_ACTIVE(unlock_pup_dq_array[dq], in ddr3_pbs_per_bit()
1253 [pbs_cmp_retry][dq], in ddr3_pbs_per_bit()
1259 DEBUG_PBS_FULL_S(" DQ: "); in ddr3_pbs_per_bit()
1260 DEBUG_PBS_FULL_D(dq, 1); in ddr3_pbs_per_bit()
1266 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_per_bit()
1267 unlock_pup_dq_array[dq] &= in ddr3_pbs_per_bit()
1268 cmp_unlock_pup_dq_array[pbs_cmp_retry][dq]; in ddr3_pbs_per_bit()
1275 /* Check which DQ is failed */ in ddr3_pbs_per_bit()
1276 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_per_bit()
1278 pup_locked |= unlock_pup_dq_array[dq]; in ddr3_pbs_per_bit()
1281 sum_pup_fail &= unlock_pup_dq_array[dq]; in ddr3_pbs_per_bit()
1284 /* If all PUPS are locked in all DQ - Break */ in ddr3_pbs_per_bit()
1330 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_per_bit()
1332 (unlock_pup_dq_array[dq], in ddr3_pbs_per_bit()
1334 DEBUG_PBS_FULL_D(dq, 1); in ddr3_pbs_per_bit()
1339 dq] = in ddr3_pbs_per_bit()
1418 u32 pup, phys_pup, dq; in ddr3_set_pbs_results() local
1440 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_set_pbs_results()
1441 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1442 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1444 if (pbs_max < skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1445 pbs_max = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1458 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_set_pbs_results()
1462 /* Set skew value for all dq */ in ddr3_set_pbs_results()
1469 DEBUG_PBS_FULL_S("DQ"); in ddr3_set_pbs_results()
1470 DEBUG_PBS_FULL_D(dq, 1); in ddr3_set_pbs_results()
1472 DEBUG_PBS_FULL_D((skew_array[(pup * DQ_NUM) + dq] - in ddr3_set_pbs_results()
1476 idx = (pup * DQ_NUM) + dq; in ddr3_set_pbs_results()
1483 ddr3_write_pup_reg(offs + pbs_dq_mapping[phys_pup][dq], in ddr3_set_pbs_results()