1 // SPDX-License-Identifier: GPL-2.0
76 	puts("\n########### LOG LEVEL 1 (D-UNIT SETUP)###########\n");  in print_dunit_setup()
79 	puts("\nStatic D-UNIT Setup:\n");  in print_dunit_setup()
82 	puts("\nDynamic(using SPD) D-UNIT Setup:\n");  in print_dunit_setup()
157 	/* Return XBAR windows 4-7 or 16-19 init configuration */  in ddr3_restore_and_set_final_windows()
161 	DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n");  in ddr3_restore_and_set_final_windows()
191 	/* Open fast path Window to - 0.5G */  in ddr3_restore_and_set_final_windows()
220 	/* Close XBAR Window 19 - Not needed */  in ddr3_save_and_set_training_windows()
221 	/* {0x000200e8}  -   Open Mbus Window - 2G */  in ddr3_save_and_set_training_windows()
224 	/* Save XBAR Windows 4-19 init configurations */  in ddr3_save_and_set_training_windows()
228 	/* Open XBAR Windows 4-7 or 16-19 for other CS */  in ddr3_save_and_set_training_windows()
268  * Name:     ddr3_init - Main DDR3 Init function
283 		DEBUG_INIT_S("DDR3 Training Error: Bad sample at reset");  in ddr3_init()
291 		DEBUG_INIT_S("DDR3 Training Error: Bad R-DIMM setup");  in ddr3_init()
308 	puts("\nDDR3 Training Sequence - Run DDR3 at ");  in print_ddr_target_freq()
346 	default:  in print_ddr_target_freq()
387 	default:  in ddr3_init_main()
399 	 * Stage 0 - Set board configuration  in ddr3_init_main()
403 		fab_opt = FAB_OPT - 1;  in ddr3_init_main()
415 		DEBUG_INIT_S("DDR3 Training Sequence - FAILED - Wrong Sample at Reset Configurations\n");  in ddr3_init_main()
454 		DEBUG_INIT_S("DDR3 Training Sequence - 2nd boot - Skip\n");  in ddr3_init_main()
459 	 * Stage 1 - Dunit Setup  in ddr3_init_main()
464 	 * For Static D-Unit Setup use must set the correct static values  in ddr3_init_main()
467 	DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static MC Init\n");  in ddr3_init_main()
490 		DEBUG_INIT_S("DDR3 Training Sequence - DRAM bus width 32Bit\n");  in ddr3_init_main()
506 		DEBUG_INIT_S("DDR3 Training Sequence - FAILED (ddr3 Dunit Setup)\n");  in ddr3_init_main()
514 	reg |= 0x4;		/* Phase 0 */  in ddr3_init_main()
516 	reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS));	/* Phase 1 */  in ddr3_init_main()
518 	reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS));	/* Phase 3 */  in ddr3_init_main()
531 	/* 0x14A8 - AXI Control Register */  in ddr3_init_main()
534 	/* 0x14A8 - AXI Control Register */  in ddr3_init_main()
540 		/* 0x14A8 - AXI Control Register */  in ddr3_init_main()
548 	 * ARMADA-370 activate DLB later at the u-boot,  in ddr3_init_main()
549 	 * Armada38x - No DLB activation at this time  in ddr3_init_main()
554 	/* WA according to eratta GL-8672902*/  in ddr3_init_main()
569 	/* WA according to eratta GL-8672902 */  in ddr3_init_main()
582 	 * Stage 2 - Training Values Setup  in ddr3_init_main()
586 	 * DRAM Init - After all the D-unit values are set, its time to init  in ddr3_init_main()
587 	 * the D-unit  in ddr3_init_main()
596 	/* ddr3 init using static parameters - HW training is disabled */  in ddr3_init_main()
597 	DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static Training Parameters\n");  in ddr3_init_main()
602 	 * If ECC is enabled, need to scrub the U-Boot area memory region -  in ddr3_init_main()
610 		DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n");  in ddr3_init_main()
615 	/* Set X-BAR windows for the training sequence */  in ddr3_init_main()
627 	DEBUG_INIT_FULL_S("DDR3 Training Sequence - HW Training Procedure\n");  in ddr3_init_main()
633 		DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n");  in ddr3_init_main()
639 	 * Stage 3 - Finish  in ddr3_init_main()
676 	DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully (S)\n");  in ddr3_init_main()
678 	DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully\n");  in ddr3_init_main()
697 	/* Read sample at reset setting */  in ddr3_get_cpu_freq()
702 	/* Read sample at reset setting */  in ddr3_get_cpu_freq()
732 	/* Read sample at reset setting */  in ddr3_get_fab_opt()
771  * Name:     ddr3_static_training_init - Init DDR3 Training with
789 	while (ddr_mode->vals[j].reg_addr != 0) {  in ddr3_static_training_init()
791 		reg_write(ddr_mode->vals[j].reg_addr,  in ddr3_static_training_init()
792 			  ddr_mode->vals[j].reg_value);  in ddr3_static_training_init()
794 		if (ddr_mode->vals[j].reg_addr ==  in ddr3_static_training_init()
806  * Name:     ddr3_get_static_mc_value - Init Memory controller with static
830  * Name:     ddr3_get_static_ddr_mode - Init Memory controller with static
872  * Name:     ddr3_static_mc_init - Init Memory controller with static parameters
888 	while (ddr_mode->regs[j].reg_addr != 0) {  in ddr3_static_mc_init()
889 		reg_write(ddr_mode->regs[j].reg_addr,  in ddr3_static_mc_init()
890 			  ddr_mode->regs[j].reg_value);  in ddr3_static_mc_init()
891 		if (ddr_mode->regs[j].reg_addr ==  in ddr3_static_mc_init()
903  * Name:     ddr3_check_config - Check user configurations: ECC/MultiCS
950  * Name:     ddr3_get_eprom_fabric - Get Fabric configuration from EPROM
973  * Name:     ddr3_cl_to_valid_cl - this return register matching CL value
975  * Args:     clValue - the value
1013 	default:  in ddr3_cl_to_valid_cl()
1019  * Name:     ddr3_cl_to_valid_cl - this return register matching CL value
1021  * Args:     clValue - the value
1058 	default:  in ddr3_valid_cl_to_cl()
1098  * mv_ctrl_rev_get - Get Marvell controller device revision number
1207 	default:  in get_target_freq()