700 	u32 *sdram_offset = (u32 *)RESUME_TRAINING_VALUES_ADDR;  in ddr3_save_training()  local
744 							(*sdram_offset) = val;  in ddr3_save_training()
745 							crc += *sdram_offset;  in ddr3_save_training()
746 							sdram_offset++;  in ddr3_save_training()
755 					*sdram_offset = val;  in ddr3_save_training()
756 					crc += *sdram_offset;  in ddr3_save_training()
757 					sdram_offset++;  in ddr3_save_training()
764 	*sdram_offset = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR);  in ddr3_save_training()
765 	crc += *sdram_offset;  in ddr3_save_training()
766 	sdram_offset++;  in ddr3_save_training()
768 	*sdram_offset = reg_read(REG_READ_DATA_READY_DELAYS_ADDR);  in ddr3_save_training()
769 	crc += *sdram_offset;  in ddr3_save_training()
770 	sdram_offset++;  in ddr3_save_training()
772 	sdram_offset = (u32 *)NUM_OF_REGISTER_ADDR;  in ddr3_save_training()
773 	*sdram_offset = regs;  in ddr3_save_training()
777 	sdram_offset = (u32 *)CHECKSUM_RESULT_ADDR;  in ddr3_save_training()
778 	*sdram_offset = crc;  in ddr3_save_training()
793 	u32 *sdram_offset = (u32 *)RESUME_TRAINING_VALUES_ADDR;  in ddr3_read_training_results()  local
802 		training_val[idx] = *sdram_offset;  in ddr3_read_training_results()
803 		crc += *sdram_offset;  in ddr3_read_training_results()
804 		sdram_offset++;  in ddr3_read_training_results()
807 	sdram_offset = (u32 *)CHECKSUM_RESULT_ADDR;  in ddr3_read_training_results()
809 	if ((*sdram_offset) == crc) {  in ddr3_read_training_results()
872 	u32 *sdram_offset = (u32 *)BOOT_INFO_ADDR;  in ddr3_check_if_resume_mode()  local
902 	magic_word = *sdram_offset;  in ddr3_check_if_resume_mode()