Lines Matching +full:max +full:- +full:freq
1 // SPDX-License-Identifier: GPL-2.0
64 puts("DDR3 Training Sequence - Ver 5.7."); in ddr3_print_version()
83 u32 freq, reg; in ddr3_hw_training() local
90 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 1\n"); in ddr3_hw_training()
104 /* Ignore ECC errors - if ECC is enabled */ in ddr3_hw_training()
152 /* first_loop_flag = 1; skip mid freq at ALP/A375 */ in ddr3_hw_training()
161 freq = dram_info.target_frequency; in ddr3_hw_training()
174 * Xor Bypass - ECC support in AXP is currently available for 1:1 in ddr3_hw_training()
184 DEBUG_MAIN_S("DDR3 Training Sequence - Run with PBS.\n"); in ddr3_hw_training()
186 DEBUG_MAIN_S("DDR3 Training Sequence - Run without PBS.\n"); in ddr3_hw_training()
191 freq = DDR_100; in ddr3_hw_training()
194 freq = DDR_300; in ddr3_hw_training()
196 if (MV_OK != ddr3_dfs_high_2_low(freq, &dram_info)) { in ddr3_hw_training()
197 /* Set low - 100Mhz DDR Frequency by HW */ in ddr3_hw_training()
198 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs High2Low)\n"); in ddr3_hw_training()
205 ddr3_write_leveling_hw_reg_dimm(freq, in ddr3_hw_training()
207 DEBUG_MAIN_S("DDR3 Training Sequence - Registered DIMM Low WL - SKIP\n"); in ddr3_hw_training()
211 ddr3_print_freq(freq); in ddr3_hw_training()
214 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 2\n"); in ddr3_hw_training()
225 * ODT - Multi CS system use SW WL, in ddr3_hw_training()
231 freq, tmp_ratio, in ddr3_hw_training()
233 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n"); in ddr3_hw_training()
238 ddr3_write_leveling_hw(freq, in ddr3_hw_training()
240 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n"); in ddr3_hw_training()
246 freq, &dram_info)) { in ddr3_hw_training()
247 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n"); in ddr3_hw_training()
251 freq, tmp_ratio, in ddr3_hw_training()
253 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n"); in ddr3_hw_training()
264 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 3\n"); in ddr3_hw_training()
268 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Loading Patterns)\n"); in ddr3_hw_training()
274 * The mainline U-Boot port of the bin_hdr DDR training code in ddr3_hw_training()
279 * Tested on the Marvell DB-MV784MP-GP board in ddr3_hw_training()
284 freq = dram_info.target_frequency; in ddr3_hw_training()
286 DEBUG_MAIN_FULL_S("DDR3 Training Sequence - DEBUG - 4\n"); in ddr3_hw_training()
294 freq = DDR_400; in ddr3_hw_training()
299 if (MV_OK != ddr3_dfs_low_2_high(freq, tmp_ratio, in ddr3_hw_training()
301 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs Low2High)\n"); in ddr3_hw_training()
306 ddr3_print_freq(freq); in ddr3_hw_training()
310 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 5\n"); in ddr3_hw_training()
316 * ODT - Multi CS system that not support Multi in ddr3_hw_training()
321 freq, tmp_ratio, &dram_info)) { in ddr3_hw_training()
322 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n"); in ddr3_hw_training()
327 freq, &dram_info)) { in ddr3_hw_training()
328 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n"); in ddr3_hw_training()
334 (freq == DDR_400)) { in ddr3_hw_training()
337 freq, &dram_info)) in ddr3_hw_training()
338 DEBUG_MAIN_S("DDR3 Training Sequence - Registered DIMM WL - SKIP\n"); in ddr3_hw_training()
342 freq, &dram_info)) { in ddr3_hw_training()
343 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n"); in ddr3_hw_training()
346 freq, tmp_ratio, &dram_info)) { in ddr3_hw_training()
347 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n"); in ddr3_hw_training()
358 ("DDR3 Training Sequence - DEBUG - 6\n"); in ddr3_hw_training()
363 * Armada 370 - Support for HCLK @ 400MHZ - must use in ddr3_hw_training()
366 if (freq == DDR_400 && dram_info.rl400_bug) { in ddr3_hw_training()
367 status = ddr3_read_leveling_sw(freq, tmp_ratio, in ddr3_hw_training()
371 ("DDR3 Training Sequence - FAILED (Read Leveling Sw)\n"); in ddr3_hw_training()
376 freq, &dram_info)) { in ddr3_hw_training()
377 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Read Leveling Hw)\n"); in ddr3_hw_training()
380 freq, tmp_ratio, in ddr3_hw_training()
382 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Read Leveling Sw)\n"); in ddr3_hw_training()
392 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 7\n"); in ddr3_hw_training()
395 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hi-Freq Sup)\n"); in ddr3_hw_training()
400 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 8\n"); in ddr3_hw_training()
410 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (PBS RX)\n"); in ddr3_hw_training()
415 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 9\n"); in ddr3_hw_training()
419 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (PBS TX)\n"); in ddr3_hw_training()
424 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 10\n"); in ddr3_hw_training()
428 } while (freq != dram_info.target_frequency); in ddr3_hw_training()
432 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (DQS Centralization RX)\n"); in ddr3_hw_training()
437 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 11\n"); in ddr3_hw_training()
441 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (DQS Centralization TX)\n"); in ddr3_hw_training()
446 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 12\n"); in ddr3_hw_training()
452 /* Need to SCRUB the DRAM memory area to load U-Boot */ in ddr3_hw_training()
465 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 13\n"); in ddr3_hw_training()
489 DEBUG_MAIN_FULL_C("Max WL Phase: ", dram_info->wl_max_phase, 2); in ddr3_set_performance_params()
490 DEBUG_MAIN_FULL_C("Min WL Phase: ", dram_info->wl_min_phase, 2); in ddr3_set_performance_params()
491 DEBUG_MAIN_FULL_C("Max RL Phase: ", dram_info->rl_max_phase, 2); in ddr3_set_performance_params()
492 DEBUG_MAIN_FULL_C("Min RL Phase: ", dram_info->rl_min_phase, 2); in ddr3_set_performance_params()
494 if (dram_info->wl_max_phase < 2) in ddr3_set_performance_params()
499 trd2rd = 0x1 + (dram_info->rl_max_phase + 1) / 2 + in ddr3_set_performance_params()
500 (dram_info->rl_max_phase + 1) % 2; in ddr3_set_performance_params()
502 tmp1 = (dram_info->rl_max_phase - dram_info->wl_min_phase) / 2 + in ddr3_set_performance_params()
503 (((dram_info->rl_max_phase - dram_info->wl_min_phase) % 2) > in ddr3_set_performance_params()
505 tmp2 = (dram_info->wl_max_phase - dram_info->rl_min_phase) / 2 + in ddr3_set_performance_params()
506 ((dram_info->wl_max_phase - dram_info->rl_min_phase) % 2 > in ddr3_set_performance_params()
571 /* If read Leveling mode - need to write to register 3 separetly */ in ddr3_write_pup_reg()
623 /* Enable SW override - Required for the ECC Pup */ in ddr3_load_patterns()
627 /* [0] = 1 - Enable SW override */ in ddr3_load_patterns()
628 /* 0x15B8 - Training SW 2 Register */ in ddr3_load_patterns()
632 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_load_patterns()
641 /* Disable SW override - Must be in a different stage */ in ddr3_load_patterns()
642 /* [0]=0 - Enable SW override */ in ddr3_load_patterns()
645 /* 0x15B8 - Training SW 2 Register */ in ddr3_load_patterns()
665 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_load_patterns()
713 tmp_cs = dram_info->cs_ena; in ddr3_save_training()
718 for (pup = 0; pup < dram_info->num_of_total_pups; in ddr3_save_training()
720 if (pup == dram_info->num_of_std_pups && in ddr3_save_training()
721 dram_info->ecc_ena) in ddr3_save_training()
822 for (idx = 0; idx < (regs - 2); idx++) { in ddr3_read_training_results()
869 int ddr3_check_if_resume_mode(MV_DRAM_INFO *dram_info, u32 freq) in ddr3_check_if_resume_mode() argument
874 if (dram_info->reg_dimm != 1) { in ddr3_check_if_resume_mode()
879 if (MV_OK != ddr3_write_leveling_hw(freq, dram_info)) { in ddr3_check_if_resume_mode()
880 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n"); in ddr3_check_if_resume_mode()
886 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Loading Patterns)\n"); in ddr3_check_if_resume_mode()
891 dram_info->cs_ena = 0x1; in ddr3_check_if_resume_mode()
894 if (MV_OK != ddr3_read_leveling_hw(freq, dram_info)) { in ddr3_check_if_resume_mode()
895 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Read Leveling Hw)\n"); in ddr3_check_if_resume_mode()
900 dram_info->cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_check_if_resume_mode()
915 u32 freq, reg; in ddr3_training_suspend_resume() local
927 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_training_suspend_resume()
933 /* [0] = 1 - Enable SW override, [4] = 1 - FIFO reset */ in ddr3_training_suspend_resume()
934 /* 0x15B8 - Training SW 2 Register */ in ddr3_training_suspend_resume()
942 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_training_suspend_resume()
945 freq = dram_info->target_frequency; in ddr3_training_suspend_resume()
947 if (MV_OK != ddr3_dfs_low_2_high(freq, tmp_ratio, dram_info)) { in ddr3_training_suspend_resume()
948 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs Low2High)\n"); in ddr3_training_suspend_resume()
952 if (dram_info->ecc_ena) { in ddr3_training_suspend_resume()
955 dram_info->num_cs = 1; in ddr3_training_suspend_resume()
956 dram_info->cs_ena = 1; in ddr3_training_suspend_resume()
974 void ddr3_print_freq(u32 freq) in ddr3_print_freq() argument
978 switch (freq) { in ddr3_print_freq()
1020 u32 *max, u32 *cs_max) in ddr3_get_min_max_read_sample_delay() argument
1025 *max = 0x0; in ddr3_get_min_max_read_sample_delay()
1036 if (delay > *max) { in ddr3_get_min_max_read_sample_delay()
1037 *max = delay; in ddr3_get_min_max_read_sample_delay()
1045 int ddr3_get_min_max_rl_phase(MV_DRAM_INFO *dram_info, u32 *min, u32 *max, in ddr3_get_min_max_rl_phase() argument
1051 *max = 0x0; in ddr3_get_min_max_rl_phase()
1053 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_get_min_max_rl_phase()
1060 if (phase > *max) in ddr3_get_min_max_rl_phase()
1061 *max = phase; in ddr3_get_min_max_rl_phase()
1073 /* {0x0000149C} - DDR Dunit ODT Control Register */ in ddr3_odt_activate()
1088 u32 min, max, cs_max; in ddr3_odt_read_dynamic_config() local
1102 ddr3_get_min_max_rl_phase(dram_info, &min, &max, cs_max); in ddr3_odt_read_dynamic_config()
1103 max_rl_phase = max; in ddr3_odt_read_dynamic_config()
1108 reg |= (((min_read_sample_delay - 1) & 0xF) << REG_ODT_ON_CTL_RD_OFFS); in ddr3_odt_read_dynamic_config()