Lines Matching +full:low +full:- +full:pass
1 // SPDX-License-Identifier: GPL-2.0
55 /* State machine for centralization - find low & high limit */
62 /* Hold centralization low results */
97 switch (dram_info->ddr_width) { in ddr3_dqs_choose_pattern()
135 DEBUG_DQS_S("DDR3 - DQS Centralization RX - Starting procedure\n"); in ddr3_dqs_centralization_rx()
141 /* [0] = 1 - Enable SW override */ in ddr3_dqs_centralization_rx()
142 /* 0x15B8 - Training SW 2 Register */ in ddr3_dqs_centralization_rx()
144 DEBUG_DQS_S("DDR3 - DQS Centralization RX - SW Override Enabled\n"); in ddr3_dqs_centralization_rx()
147 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_dqs_centralization_rx()
151 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_rx()
152 DEBUG_DQS_FULL_C("DDR3 - DQS Centralization RX - CS - ", in ddr3_dqs_centralization_rx()
155 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_dqs_centralization_rx()
157 /* ECC Support - Switch ECC Mux on ecc=1 */ in ddr3_dqs_centralization_rx()
160 reg |= (dram_info->ecc_ena * in ddr3_dqs_centralization_rx()
165 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - ECC Mux Enabled\n"); in ddr3_dqs_centralization_rx()
167 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - ECC Mux Disabled\n"); in ddr3_dqs_centralization_rx()
169 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - Find all limits\n"); in ddr3_dqs_centralization_rx()
176 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - Start calculating center\n"); in ddr3_dqs_centralization_rx()
186 /* ECC Support - Disable ECC MUX */ in ddr3_dqs_centralization_rx()
191 /* Disable SW override - Must be in a different stage */ in ddr3_dqs_centralization_rx()
192 /* [0]=0 - Enable SW override */ in ddr3_dqs_centralization_rx()
195 /* 0x15B8 - Training SW 2 Register */ in ddr3_dqs_centralization_rx()
217 DEBUG_DQS_S("DDR3 - DQS Centralization TX - Starting procedure\n"); in ddr3_dqs_centralization_tx()
223 /* [0] = 1 - Enable SW override */ in ddr3_dqs_centralization_tx()
224 /* 0x15B8 - Training SW 2 Register */ in ddr3_dqs_centralization_tx()
226 DEBUG_DQS_S("DDR3 - DQS Centralization TX - SW Override Enabled\n"); in ddr3_dqs_centralization_tx()
229 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_dqs_centralization_tx()
233 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_tx()
234 DEBUG_DQS_FULL_C("DDR3 - DQS Centralization TX - CS - ", in ddr3_dqs_centralization_tx()
236 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_dqs_centralization_tx()
237 /* ECC Support - Switch ECC Mux on ecc=1 */ in ddr3_dqs_centralization_tx()
240 reg |= (dram_info->ecc_ena * in ddr3_dqs_centralization_tx()
245 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization TX - ECC Mux Enabled\n"); in ddr3_dqs_centralization_tx()
247 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization TX - ECC Mux Disabled\n"); in ddr3_dqs_centralization_tx()
249 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization TX - Find all limits\n"); in ddr3_dqs_centralization_tx()
256 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization TX - Start calculating center\n"); in ddr3_dqs_centralization_tx()
266 /* ECC Support - Disable ECC MUX */ in ddr3_dqs_centralization_tx()
271 /* Disable SW override - Must be in a different stage */ in ddr3_dqs_centralization_tx()
272 /* [0]=0 - Enable SW override */ in ddr3_dqs_centralization_tx()
275 /* 0x15B8 - Training SW 2 Register */ in ddr3_dqs_centralization_tx()
304 u32 adll_start_val; /* adll start loop value - for rx or tx limit */ in ddr3_find_adll_limits()
306 u32 low_limit; /* holds found Low Limit */ in ddr3_find_adll_limits()
313 u32 adll_end_val; /* adll end of loop val - for rx or tx limit */ in ddr3_find_adll_limits()
321 max_pup = (ecc + (1 - ecc) * dram_info->num_of_std_pups); in ddr3_find_adll_limits()
323 DEBUG_DQS_FULL_S("DDR3 - DQS Find Limits - Starting Find ADLL Limits\n"); in ddr3_find_adll_limits()
334 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_find_adll_limits()
352 /* Loop - use different pattern for each victim_dq */ in ddr3_find_adll_limits()
354 DEBUG_DQS_FULL_C("DDR3 - DQS Find Limits - Victim DQ - ", in ddr3_find_adll_limits()
359 * 1. fail and didn't get pass in earlier compares. in ddr3_find_adll_limits()
360 * 2. pass compare in ddr3_find_adll_limits()
361 * 3. fail after pass - end state. in ddr3_find_adll_limits()
363 * was in the pass stage. in ddr3_find_adll_limits()
389 DEBUG_DQS_FULL_C("DDR3 - DQS Find Limits - Setting ADLL to ", in ddr3_find_adll_limits()
394 dram_info->wl_val[cs] in ddr3_find_adll_limits()
395 [pup * (1 - ecc) + ecc * ECC_PUP] in ddr3_find_adll_limits()
406 /* '1' - means pup failed, '0' - means pup pass */ in ddr3_find_adll_limits()
427 DEBUG_DQS_FULL_C("DDR3 - DQS Find Limits - UnlockPup: ", in ddr3_find_adll_limits()
429 DEBUG_DQS_FULL_C("DDR3 - DQS Find Limits - NewUnlockPup: ", in ddr3_find_adll_limits()
435 DEBUG_DQS_FULL_C("DDR3 - DQS Find Limits - Skipping pup ", in ddr3_find_adll_limits()
451 DEBUG_DQS_S("DDR3 - DQS Find Limits - PASS to FAIL: CS - "); in ddr3_find_adll_limits()
453 DEBUG_DQS_S(", DQ - "); in ddr3_find_adll_limits()
455 DEBUG_DQS_S(", Pup - "); in ddr3_find_adll_limits()
457 DEBUG_DQS_S(", ADLL - "); in ddr3_find_adll_limits()
478 /* RX - found upper limit */ in ddr3_find_adll_limits()
480 (curr_adll - 1)) { in ddr3_find_adll_limits()
482 curr_adll - 1; in ddr3_find_adll_limits()
488 /* TX - found lower limit */ in ddr3_find_adll_limits()
530 /* Found end of window - lock the pup */ in ddr3_find_adll_limits()
535 /* Probably false pass - reset status */ in ddr3_find_adll_limits()
562 /* Current compare result == pass */ in ddr3_find_adll_limits()
566 DEBUG_DQS_S("DDR3 - DQS Find Limits - FAIL to PASS: CS - "); in ddr3_find_adll_limits()
568 DEBUG_DQS_S(", DQ - "); in ddr3_find_adll_limits()
570 DEBUG_DQS_S(", Pup - "); in ddr3_find_adll_limits()
572 DEBUG_DQS_S(", ADLL - "); in ddr3_find_adll_limits()
593 /* RX - found low limit */ in ddr3_find_adll_limits()
599 /* TX - found high limit */ in ddr3_find_adll_limits()
611 DEBUG_DQS_FULL_S("DDR3 - DQS Find Limits - found PUP limit\n"); in ddr3_find_adll_limits()
617 * one phase - ADLL) dqs RX / TX delay (for all un in ddr3_find_adll_limits()
623 curr_adll--; in ddr3_find_adll_limits()
631 DEBUG_DQS_C("DDR3 - DQS Find Limits - Pups that didn't reached end of the state machine: ", in ddr3_find_adll_limits()
638 /* ERROR - found fail for all window size */ in ddr3_find_adll_limits()
639 DEBUG_DQS_S("DDR3 - DQS Find Limits - Got FAIL for the complete range on pup - "); in ddr3_find_adll_limits()
644 /* For debug - set min limit to illegal limit */ in ddr3_find_adll_limits()
649 * PASS - the limit is the min in ddr3_find_adll_limits()
661 DEBUG_DQS_S("DDR3 - DQS Find Limits - DQ values per victim results:\n"); in ddr3_find_adll_limits()
664 DEBUG_DQS_S("Victim DQ-"); in ddr3_find_adll_limits()
666 DEBUG_DQS_S(", PUP-"); in ddr3_find_adll_limits()
669 DEBUG_DQS_S(", DQ-"); in ddr3_find_adll_limits()
671 DEBUG_DQS_S(",S-"); in ddr3_find_adll_limits()
674 DEBUG_DQS_S(",E-"); in ddr3_find_adll_limits()
709 DEBUG_PER_DQ_S("\n########## LOG LEVEL 3(Windows margins per-DQ) ##########\n"); in ddr3_find_adll_limits()
711 DEBUG_PER_DQ_C("DDR3 - TX CS: ", cs, 1); in ddr3_find_adll_limits()
713 DEBUG_PER_DQ_C("DDR3 - RX CS: ", cs, 1); in ddr3_find_adll_limits()
732 DEBUG_PER_DQ_S(" DQ's LOW HIGH WIN-SIZE\n"); in ddr3_find_adll_limits()
747 DEBUG_PER_DQ_D(analog_pbs[victim_dq][pup][dq][1], 2); /* low value */ in ddr3_find_adll_limits()
751 …DEBUG_PER_DQ_D(analog_pbs[victim_dq][pup][dq][0] - analog_pbs[victim_dq][pup][dq][1], 2); /* win-s… in ddr3_find_adll_limits()
754 DEBUG_PER_DQ_D(analog_pbs[victim_dq][pup][dq][0], 2); /* low value */ in ddr3_find_adll_limits()
756 DEBUG_PER_DQ_D((analog_pbs[victim_dq][pup][dq][1] - 1), 2); /* high value */ in ddr3_find_adll_limits()
758 …DEBUG_PER_DQ_D(analog_pbs[victim_dq][pup][dq][1] - analog_pbs[victim_dq][pup][dq][0], 2); /* win-s… in ddr3_find_adll_limits()
767 DEBUG_DQS_S("DDR3 - DQS TX - Find Limits - DQ values Summary:\n"); in ddr3_find_adll_limits()
769 DEBUG_DQS_S("DDR3 - DQS RX - Find Limits - DQ values Summary:\n"); in ddr3_find_adll_limits()
773 DEBUG_DQS_S("PUP-"); in ddr3_find_adll_limits()
776 DEBUG_DQS_S(", DQ-"); in ddr3_find_adll_limits()
778 DEBUG_DQS_S(",S-"); in ddr3_find_adll_limits()
780 DEBUG_DQS_S(",E-"); in ddr3_find_adll_limits()
787 DEBUG_DQS_S("DDR3 - DQS TX - Find Limits - DQ values Summary:\n"); in ddr3_find_adll_limits()
789 DEBUG_DQS_S("DDR3 - DQS RX - Find Limits - DQ values Summary:\n"); in ddr3_find_adll_limits()
795 DEBUG_DQS_S("DDR3 - DQS8"); in ddr3_find_adll_limits()
797 DEBUG_DQS_S("DDR3 - DQS"); in ddr3_find_adll_limits()
802 DEBUG_DQS_S(", DQ-"); in ddr3_find_adll_limits()
804 DEBUG_DQS_S("::S-"); in ddr3_find_adll_limits()
806 DEBUG_DQS_S(",E-"); in ddr3_find_adll_limits()
812 DEBUG_DQS_S("DDR3 - DQS Find Limits - Ended\n"); in ddr3_find_adll_limits()
819 * Desc: Check window High & Low limits.
822 * low_limit window low limit
831 DEBUG_DQS_FULL_S("DDR3 - DQS Check Win Limits - Starting\n"); in ddr3_check_window_limits()
834 DEBUG_DQS_S("DDR3 - DQS Check Win Limits - Pup "); in ddr3_check_window_limits()
836 DEBUG_DQS_S(" Low Limit grater than High Limit\n"); in ddr3_check_window_limits()
842 * Check that window size is valid, if not it was probably false pass in ddr3_check_window_limits()
845 if ((high_limit - low_limit) < MIN_WIN_SIZE) { in ddr3_check_window_limits()
848 * pass in ddr3_check_window_limits()
852 DEBUG_DQS_S("DDR3 - DQS Check Win Limits - Pup "); in ddr3_check_window_limits()
856 } else if ((high_limit - low_limit) > ADLL_MAX) { in ddr3_check_window_limits()
859 DEBUG_DQS_S("DDR3 - DQS Check Win Limits - Pup "); in ddr3_check_window_limits()
869 DEBUG_DQS_FULL_S("DDR3 - DQS Check Win Limits - Pup "); in ddr3_check_window_limits()
871 DEBUG_DQS_FULL_C(" window size is ", (high_limit - low_limit), in ddr3_check_window_limits()
895 max_pup = (ecc + (1 - ecc) * dram_info->num_of_std_pups); in ddr3_center_calc()
901 * Special pattern Low limit search - relevant only in ddr3_center_calc()
902 * for Rx, win size < threshold and low limit = 0 in ddr3_center_calc()
904 if (((centralization_high_limit[pup] - in ddr3_center_calc()
911 * Special pattern High limit search - relevant only in ddr3_center_calc()
914 if (((centralization_high_limit[pup] - in ddr3_center_calc()
921 /* Run special pattern Low limit search - for relevant pup */ in ddr3_center_calc()
923 DEBUG_DQS_S("DDR3 - DQS Center Calc - Entering special pattern I for Low limit search\n"); in ddr3_center_calc()
930 /* Run special pattern High limit search - for relevant pup */ in ddr3_center_calc()
932 DEBUG_DQS_S("DDR3 - DQS Center Calc - Entering special pattern II for High limit search\n"); in ddr3_center_calc()
945 * Desc: Execute special pattern low limit search.
954 u32 victim_dq; /* loop index - victim DQ */ in ddr3_special_pattern_i_search()
958 u32 first_fail; /* bit array - of pups that get first fail */ in ddr3_special_pattern_i_search()
960 u32 pass_pup; /* bit array of compare pass pup */ in ddr3_special_pattern_i_search()
966 DEBUG_DQS_S("DDR3 - DQS - Special Pattern I Search - Starting\n"); in ddr3_special_pattern_i_search()
968 max_pup = ecc + (1 - ecc) * dram_info->num_of_std_pups; in ddr3_special_pattern_i_search()
974 /* Run special pattern for all DQ - use the same pattern */ in ddr3_special_pattern_i_search()
997 * un-locked MC use the special pattern mask in ddr3_special_pattern_i_search()
1011 DEBUG_DQS_S("DDR3 - DQS - Special I - ADLL value is: "); in ddr3_special_pattern_i_search()
1020 DEBUG_DQS_S("DDR3 - DQS - Special I - Some Pup passed!\n"); in ddr3_special_pattern_i_search()
1027 /* Get pass pups */ in ddr3_special_pattern_i_search()
1033 /* keep min value of ADLL max value - current adll */ in ddr3_special_pattern_i_search()
1036 (ADLL_MAX - in ddr3_special_pattern_i_search()
1041 ("DDR3 - DQS - Special I - Pup - ", in ddr3_special_pattern_i_search()
1053 (-1) * in ddr3_special_pattern_i_search()
1057 ("DDR3 - DQS - Special I - Pup - ", in ddr3_special_pattern_i_search()
1060 (" Changed Low limit to ", in ddr3_special_pattern_i_search()
1071 * reach maximum if reach max value - lock the pup in ddr3_special_pattern_i_search()
1072 * if not - increment (Move to right one phase - ADLL) in ddr3_special_pattern_i_search()
1081 /* reach maximum - lock the pup */ in ddr3_special_pattern_i_search()
1082 DEBUG_DQS_C("DDR3 - DQS - Special I - reach maximum - lock pup ", in ddr3_special_pattern_i_search()
1086 /* Didn't reach maximum - increment ADLL */ in ddr3_special_pattern_i_search()
1115 u32 victim_dq; /* loop index - victim DQ */ in ddr3_special_pattern_ii_search()
1119 u32 first_fail; /* bit array - of pups that get first fail */ in ddr3_special_pattern_ii_search()
1121 u32 pass_pup; /* bit array of compare pass pup */ in ddr3_special_pattern_ii_search()
1127 DEBUG_DQS_S("DDR3 - DQS - Special Pattern II Search - Starting\n"); in ddr3_special_pattern_ii_search()
1129 max_pup = (ecc + (1 - ecc) * dram_info->num_of_std_pups); in ddr3_special_pattern_ii_search()
1137 /* run special pattern for all DQ - use the same pattern */ in ddr3_special_pattern_ii_search()
1156 * un-locked MC use the special pattern mask in ddr3_special_pattern_ii_search()
1167 DEBUG_DQS_S("DDR3 - DQS - Special II - ADLL value is "); in ddr3_special_pattern_ii_search()
1176 DEBUG_DQS_S("DDR3 - DQS - Special II - Some Pup passed!\n"); in ddr3_special_pattern_ii_search()
1184 /* Get pass pups */ in ddr3_special_pattern_ii_search()
1190 /* keep min value of ADLL max value - current adll */ in ddr3_special_pattern_ii_search()
1194 DEBUG_DQS_C("DDR3 - DQS - Special II - Pup - ", in ddr3_special_pattern_ii_search()
1209 ("DDR3 - DQS - Special II - Pup - ", in ddr3_special_pattern_ii_search()
1223 * reach maximum if reach max value - lock the pup in ddr3_special_pattern_ii_search()
1224 * if not - increment (Move to right one phase - ADLL) in ddr3_special_pattern_ii_search()
1232 /* Reach maximum - lock the pup */ in ddr3_special_pattern_ii_search()
1233 DEBUG_DQS_C("DDR3 - DQS - Special II - reach maximum - lock pup ", in ddr3_special_pattern_ii_search()
1237 /* Didn't reach maximum - increment ADLL */ in ddr3_special_pattern_ii_search()
1268 max_pup = (ecc + (1 - ecc) * dram_info->num_of_std_pups); in ddr3_set_dqs_centralization_results()
1273 DEBUG_DQS_RESULTS_C("DDR3 - DQS TX - Set Dqs Centralization Results - CS: ", in ddr3_set_dqs_centralization_results()
1276 DEBUG_DQS_RESULTS_C("DDR3 - DQS RX - Set Dqs Centralization Results - CS: ", in ddr3_set_dqs_centralization_results()
1281 DEBUG_DQS_RESULTS_S("\nDQS LOW HIGH WIN-SIZE Set\n"); in ddr3_set_dqs_centralization_results()
1287 pup_num = pup * (1 - ecc) + ecc * ECC_PUP; in ddr3_set_dqs_centralization_results()
1295 DEBUG_DQS_RESULTS_D(centralization_high_limit[pup] - in ddr3_set_dqs_centralization_results()
1303 …DEBUG_DQS_RESULTS_S("DDR3 - DQS - Setting ADLL value for Pup to MIN (since it was lower than 0)\n"… in ddr3_set_dqs_centralization_results()
1308 …DEBUG_DQS_RESULTS_S("DDR3 - DQS - Setting ADLL value for Pup to MAX (since it was higher than 31)\… in ddr3_set_dqs_centralization_results()
1314 dram_info->wl_val[cs][pup_num][D]); in ddr3_set_dqs_centralization_results()
1335 if (dram_info->cs_ena & (1 << cs)) { in ddr3_load_dqs_patterns()
1338 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_load_dqs_patterns()
1357 /* Init special-killer pattern */ in ddr3_load_dqs_patterns()