Lines Matching +full:auto +full:- +full:detection

1 /* SPDX-License-Identifier: GPL-2.0 */
14  * Level 1: Provides the D-Unit setup (SPD/Static configuration)
35  * DDR_TARGET_FABRIC   - Set desired fabric configuration
37  * DRAM_ECC            - Set ECC support 1/0
38  * BUS_WIDTH           - 64/32 bit
39  * CONFIG_SPD_EEPROM   - Enables auto detection of DIMMs and their timing values
40  * DQS_CLK_ALIGNED     - Set this if CLK and DQS signals are aligned on board
41  * MIXED_DIMM_STATIC   - Mixed DIMM + On board devices support (ODT registers
43  * DDR3_TRAINING_DEBUG - Debug prints of internal code
79  * DRAM_2T - Set Desired 2T Mode - 0 - 1T, 0x1 - 2T, 0x2 - 3T
80  * DIMM_CS_BITMAP - bitmap representing the optional CS in DIMMs
92  * U_BOOT_START_ADDR, U_BOOT_SCRUB_SIZE - relevant when using ECC and need
101  * Registered DIMM Support - In case registered DIMM is attached,
103  * (see JEDEC - JESD82-29A "Definition of the SSTE32882 Registering Clock
109  * RC3-RC5 - taken from SPD
141  * AUTO_DETECTION_SUPPORT - relevant ONLY for Marvell DB boards.
142  * Enables I2C auto detection different options