Lines Matching +full:0 +full:- +full:rc3

1 /* SPDX-License-Identifier: GPL-2.0 */
12  * Level 0: Provides an error code in a case of failure, RL, WL errors
14  * Level 1: Provides the D-Unit setup (SPD/Static configuration)
22 #define	DDR3_LOG_LEVEL	0
35  * DDR_TARGET_FABRIC   - Set desired fabric configuration
37  * DRAM_ECC            - Set ECC support 1/0
38  * BUS_WIDTH           - 64/32 bit
39  * CONFIG_SPD_EEPROM   - Enables auto detection of DIMMs and their timing values
40  * DQS_CLK_ALIGNED     - Set this if CLK and DQS signals are aligned on board
41  * MIXED_DIMM_STATIC   - Mixed DIMM + On board devices support (ODT registers
43  * DDR3_TRAINING_DEBUG - Debug prints of internal code
50 #define DRAM_ECC				0
61 #define DDR3_TRAINING_DEBUG			0
62 #define REG_DIMM_SKIP_WL			0
79  * DRAM_2T - Set Desired 2T Mode - 0 - 1T, 0x1 - 2T, 0x2 - 3T
80  * DIMM_CS_BITMAP - bitmap representing the optional CS in DIMMs
81  * (0xF=CS0+CS1+CS2+CS3, 0xC=CS2+CS3...)
83 #define DRAM_2T					0x0
84 #define DIMM_CS_BITMAP				0xF
92  * U_BOOT_START_ADDR, U_BOOT_SCRUB_SIZE - relevant when using ECC and need
95 #define TRAINING_SIZE				0x20000
96 #define U_BOOT_START_ADDR			0
97 #define U_BOOT_SCRUB_SIZE			0x1000000 /* TRAINING_SIZE */
101  * Registered DIMM Support - In case registered DIMM is attached,
103  * (see JEDEC - JESD82-29A "Definition of the SSTE32882 Registering Clock
109  * RC3-RC5 - taken from SPD
115 #define RDIMM_RC0				0
116 #define RDIMM_RC1				0
117 #define RDIMM_RC2				0
118 #define RDIMM_RC8				0
119 #define RDIMM_RC9				0
120 #define RDIMM_RC10				0x2
121 #define RDIMM_RC11				0x0
141  * AUTO_DETECTION_SUPPORT - relevant ONLY for Marvell DB boards.