Lines Matching +full:time +full:- +full:based
1 /* SPDX-License-Identifier: GPL-2.0 */
96 MV_DDR_CFG_DEFAULT, /* based on data in mv_ddr_topology_map structure */
97 MV_DDR_CFG_SPD, /* based on data in spd */
98 MV_DDR_CFG_USER, /* based on data from user */
99 MV_DDR_CFG_STATIC, /* based on data from user in register-value format */
116 MV_DDR_TCK_AVG_MIN, /* sdram min cycle time (t ck avg min) */
117 MV_DDR_TAA_MIN, /* min cas latency time (t aa min) */
118 MV_DDR_TRFC1_MIN, /* min refresh recovery delay time (t rfc1 min) */
119 MV_DDR_TWR_MIN, /* min write recovery time (t wr min) */
120 MV_DDR_TRCD_MIN, /* min ras to cas delay time (t rcd min) */
121 MV_DDR_TRP_MIN, /* min row precharge delay time (t rp min) */
122 MV_DDR_TRC_MIN, /* min active to active/refresh delay time (t rc min) */
123 MV_DDR_TRAS_MIN, /* min active to precharge delay time (t ras min) */
124 MV_DDR_TRRD_S_MIN, /* min activate to activate delay time (t rrd_s min), diff bank group */
125 MV_DDR_TRRD_L_MIN, /* min activate to activate delay time (t rrd_l min), same bank group */
126 MV_DDR_TCCD_L_MIN, /* min cas to cas delay time (t ccd_l min), same bank group */
127 MV_DDR_TFAW_MIN, /* min four activate window delay time (t faw min) */
128 MV_DDR_TWTR_S_MIN, /* min write to read time (t wtr s min), diff bank group */
129 MV_DDR_TWTR_L_MIN, /* min write to read time (t wtr l min), same bank group */
155 MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* 60-Ohm; RZQ = 240-Ohm */
156 MV_DDR_RTT_NOM_PARK_RZQ_DIV2, /* 120-Ohm; RZQ = 240-Ohm */
157 MV_DDR_RTT_NOM_PARK_RZQ_DIV6, /* 40-Ohm; RZQ = 240-Ohm */
158 MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* 240-Ohm; RZQ = 240-Ohm */
159 MV_DDR_RTT_NOM_PARK_RZQ_DIV5, /* 48-Ohm; RZQ = 240-Ohm */
160 MV_DDR_RTT_NOM_PARK_RZQ_DIV3, /* 80-Ohm; RZQ = 240-Ohm */
161 MV_DDR_RTT_NOM_PARK_RZQ_DIV7, /* 34-Ohm; RZQ = 240-Ohm */
167 MV_DDR_RTT_WR_RZQ_DIV2, /* 120-Ohm; RZQ = 240-Ohm */
168 MV_DDR_RTT_WR_RZQ_DIV1, /* 240-Ohm; RZQ = 240-Ohm */
170 MV_DDR_RTT_WR_RZQ_DIV3, /* 80-Ohm; RZQ = 240-Ohm */
175 MV_DDR_DIC_RZQ_DIV7, /* 34-Ohm; RZQ = 240-Ohm */
176 MV_DDR_DIC_RZQ_DIV5, /* 48-Ohm; RZQ = 240-Ohm */