1 // SPDX-License-Identifier: GPL-2.0
17  * 2. U-Boot modifies internal registers base to 0xf100000,
165 	1800			/* 30 - 0x1E */
214 	return ((((10000 * reg) / 21445) * 1000) - 272674) / 1000;  in ddr3_ctrl_get_junc_temp()
234 	freq_config_info->bw_per_freq = a38x_bw_per_freq[freq];  in ddr3_tip_a38x_get_freq_config()
235 	freq_config_info->rate_per_freq = a38x_rate_per_freq[freq];  in ddr3_tip_a38x_get_freq_config()
236 	freq_config_info->is_supported = 1;  in ddr3_tip_a38x_get_freq_config()
359  * Args:     dev_num     - device number
360  *           enable        - whether to enable or disable the server
562 	info_ptr->device_id = 0x6900;  in ddr3_tip_a38x_get_device_info()
564 	info_ptr->device_id = 0x6800;  in ddr3_tip_a38x_get_device_info()
566 	info_ptr->ck_delay = ck_delay;  in ddr3_tip_a38x_get_device_info()
623 			VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i);  in prfa_read()
687 	enum mv_ddr_freq ddr_freq = tm->interface_params[0].memory_freq;  in mv_ddr_training_mask_set()
730  * 1 - internal controller
731  * 2 - external controller
845 	dunit_write(0x1524, (1 << 15), ((ddr3_tip_clock_mode(frequency) - 1) << 15));  in ddr3_tip_a38x_set_divider()
892 	if (tm->interface_params[0].memory_freq != MV_DDR_FREQ_SAR)  in mv_ddr_early_init()
924 	/* Set half bus width */  in ddr3_silicon_post_init()
925 	if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask)) {  in ddr3_silicon_post_init()
1008 	 * so bit 15 in 0x1400, that means if whole bus used or only half,  in ddr3_calc_mem_cs_size()
1050 				[tm->interface_params[0].memory_size];  in ddr3_fast_path_dynamic_cs_size_config()
1054 				 * 16bit mem device can be twice more - no need  in ddr3_fast_path_dynamic_cs_size_config()
1073 			reg |= (cs_mem_size - 1) & 0xffff0000;  in ddr3_fast_path_dynamic_cs_size_config()
1090 			/* if the sum less than 2 G - calculate the value */  in ddr3_fast_path_dynamic_cs_size_config()
1113 	/* Return XBAR windows 4-7 or 16-19 init configuration */  in ddr3_restore_and_set_final_windows()
1117 	printf("%s Training Sequence - Switching XBAR Window to FastPath Window\n",  in ddr3_restore_and_set_final_windows()
1132 	/* Open fast path Window to - 0.5G */  in ddr3_restore_and_set_final_windows()
1160 	cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask;  in ddr3_save_and_set_training_windows()
1162 	/* Close XBAR Window 19 - Not needed */  in ddr3_save_and_set_training_windows()
1163 	/* {0x000200e8}  -   Open Mbus Window - 2G */  in ddr3_save_and_set_training_windows()
1166 	/* Save XBAR Windows 4-19 init configurations */  in ddr3_save_and_set_training_windows()
1170 	/* Open XBAR Windows 4-7 or 16-19 for other CS */  in ddr3_save_and_set_training_windows()
1249 		printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type);  in mv_ddr_pre_training_soc_config()
1278 	/* 0x14a8 - AXI Control Register */  in mv_ddr_pre_training_soc_config()
1282 	 * Stage 2 - Training Values Setup  in mv_ddr_pre_training_soc_config()
1284 	/* Set X-BAR windows for the training sequence */  in mv_ddr_pre_training_soc_config()
1352 		printf("DDR3 init controller - FAILED 0x%x\n", status);  in mv_ddr_mc_config()
1356 		printf("DDR3 init_sequence - FAILED 0x%x\n", status);  in mv_ddr_mc_config()
1411 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in ddr3_tip_configure_phy()
1413 		VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);  in ddr3_tip_configure_phy()
1418 				VALIDATE_BUS_ACTIVE(tm->bus_act_mask, phy_id);  in ddr3_tip_configure_phy()
1419 				/* Vref & clamp */  in ddr3_tip_configure_phy()