Lines Matching +full:switching +full:- +full:freq
1 // SPDX-License-Identifier: GPL-2.0
17 * 2. U-Boot modifies internal registers base to 0xf100000,
165 1800 /* 30 - 0x1E */
185 enum mv_ddr_freq freq);
214 return ((((10000 * reg) / 21445) * 1000) - 272674) / 1000; in ddr3_ctrl_get_junc_temp()
224 static int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum mv_ddr_freq freq, in ddr3_tip_a38x_get_freq_config() argument
228 if (a38x_bw_per_freq[freq] == 0xff) in ddr3_tip_a38x_get_freq_config()
234 freq_config_info->bw_per_freq = a38x_bw_per_freq[freq]; in ddr3_tip_a38x_get_freq_config()
235 freq_config_info->rate_per_freq = a38x_rate_per_freq[freq]; in ddr3_tip_a38x_get_freq_config()
236 freq_config_info->is_supported = 1; in ddr3_tip_a38x_get_freq_config()
359 * Args: dev_num - device number
360 * enable - whether to enable or disable the server
388 static int mv_ddr_sar_freq_get(int dev_num, enum mv_ddr_freq *freq) in mv_ddr_sar_freq_get() argument
403 ("Warning: Unsupported freq mode for 333Mhz configured(%d)\n", in mv_ddr_sar_freq_get()
407 *freq = MV_DDR_FREQ_333; in mv_ddr_sar_freq_get()
411 ("Warning: Unsupported freq mode for 400Mhz configured(%d)\n", in mv_ddr_sar_freq_get()
415 *freq = MV_DDR_FREQ_400; in mv_ddr_sar_freq_get()
419 ("Warning: Unsupported freq mode for 533Mhz configured(%d)\n", in mv_ddr_sar_freq_get()
423 *freq = MV_DDR_FREQ_533; in mv_ddr_sar_freq_get()
426 *freq = MV_DDR_FREQ_600; in mv_ddr_sar_freq_get()
431 ("Warning: Unsupported freq mode for 667Mhz configured(%d)\n", in mv_ddr_sar_freq_get()
435 *freq = MV_DDR_FREQ_667; in mv_ddr_sar_freq_get()
440 ("Warning: Unsupported freq mode for 800Mhz configured(%d)\n", in mv_ddr_sar_freq_get()
444 *freq = MV_DDR_FREQ_800; in mv_ddr_sar_freq_get()
447 *freq = MV_DDR_FREQ_933; in mv_ddr_sar_freq_get()
450 *freq = MV_DDR_FREQ_900; in mv_ddr_sar_freq_get()
453 *freq = MV_DDR_FREQ_933; in mv_ddr_sar_freq_get()
456 *freq = 0; in mv_ddr_sar_freq_get()
462 *freq = MV_DDR_FREQ_400; in mv_ddr_sar_freq_get()
465 *freq = MV_DDR_FREQ_533; in mv_ddr_sar_freq_get()
468 *freq = MV_DDR_FREQ_800; in mv_ddr_sar_freq_get()
471 *freq = MV_DDR_FREQ_900; in mv_ddr_sar_freq_get()
474 *freq = 0; in mv_ddr_sar_freq_get()
482 static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum mv_ddr_freq *freq) in ddr3_tip_a38x_get_medium_freq() argument
497 /* Medium is same as TF to run PBS in this freq */ in ddr3_tip_a38x_get_medium_freq()
498 *freq = MV_DDR_FREQ_333; in ddr3_tip_a38x_get_medium_freq()
502 /* Medium is same as TF to run PBS in this freq */ in ddr3_tip_a38x_get_medium_freq()
503 *freq = MV_DDR_FREQ_400; in ddr3_tip_a38x_get_medium_freq()
507 /* Medium is same as TF to run PBS in this freq */ in ddr3_tip_a38x_get_medium_freq()
508 *freq = MV_DDR_FREQ_533; in ddr3_tip_a38x_get_medium_freq()
514 *freq = MV_DDR_FREQ_333; in ddr3_tip_a38x_get_medium_freq()
519 *freq = MV_DDR_FREQ_400; in ddr3_tip_a38x_get_medium_freq()
522 *freq = MV_DDR_FREQ_300; in ddr3_tip_a38x_get_medium_freq()
525 *freq = MV_DDR_FREQ_360; in ddr3_tip_a38x_get_medium_freq()
528 *freq = MV_DDR_FREQ_400; in ddr3_tip_a38x_get_medium_freq()
531 *freq = 0; in ddr3_tip_a38x_get_medium_freq()
537 /* Medium is same as TF to run PBS in this freq */ in ddr3_tip_a38x_get_medium_freq()
538 *freq = MV_DDR_FREQ_400; in ddr3_tip_a38x_get_medium_freq()
541 /* Medium is same as TF to run PBS in this freq */ in ddr3_tip_a38x_get_medium_freq()
542 *freq = MV_DDR_FREQ_533; in ddr3_tip_a38x_get_medium_freq()
545 *freq = MV_DDR_FREQ_400; in ddr3_tip_a38x_get_medium_freq()
548 *freq = MV_DDR_FREQ_360; in ddr3_tip_a38x_get_medium_freq()
551 *freq = 0; in ddr3_tip_a38x_get_medium_freq()
562 info_ptr->device_id = 0x6900; in ddr3_tip_a38x_get_device_info()
564 info_ptr->device_id = 0x6800; in ddr3_tip_a38x_get_device_info()
566 info_ptr->ck_delay = ck_delay; in ddr3_tip_a38x_get_device_info()
623 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i); in prfa_read()
687 enum mv_ddr_freq ddr_freq = tm->interface_params[0].memory_freq; in mv_ddr_training_mask_set()
730 * 1 - internal controller
731 * 2 - external controller
744 u32 freq = mv_ddr_freq_get(frequency); in ddr3_tip_a38x_set_divider() local
753 /* get VCO freq index */ in ddr3_tip_a38x_set_divider()
761 divider = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val] / freq; in ddr3_tip_a38x_set_divider()
763 divider = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val] / freq; in ddr3_tip_a38x_set_divider()
765 if ((async_mode_at_tf == 1) && (freq > 400)) { in ddr3_tip_a38x_set_divider()
845 dunit_write(0x1524, (1 << 15), ((ddr3_tip_clock_mode(frequency) - 1) << 15)); in ddr3_tip_a38x_set_divider()
892 if (tm->interface_params[0].memory_freq != MV_DDR_FREQ_SAR) in mv_ddr_early_init()
925 if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask)) { in ddr3_silicon_post_init()
936 enum mv_ddr_freq freq; in mv_ddr_init_freq_get() local
938 mv_ddr_sar_freq_get(0, &freq); in mv_ddr_init_freq_get()
940 return freq; in mv_ddr_init_freq_get()
1050 [tm->interface_params[0].memory_size]; in ddr3_fast_path_dynamic_cs_size_config()
1054 * 16bit mem device can be twice more - no need in ddr3_fast_path_dynamic_cs_size_config()
1073 reg |= (cs_mem_size - 1) & 0xffff0000; in ddr3_fast_path_dynamic_cs_size_config()
1090 /* if the sum less than 2 G - calculate the value */ in ddr3_fast_path_dynamic_cs_size_config()
1113 /* Return XBAR windows 4-7 or 16-19 init configuration */ in ddr3_restore_and_set_final_windows()
1117 printf("%s Training Sequence - Switching XBAR Window to FastPath Window\n", in ddr3_restore_and_set_final_windows()
1132 /* Open fast path Window to - 0.5G */ in ddr3_restore_and_set_final_windows()
1160 cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask; in ddr3_save_and_set_training_windows()
1162 /* Close XBAR Window 19 - Not needed */ in ddr3_save_and_set_training_windows()
1163 /* {0x000200e8} - Open Mbus Window - 2G */ in ddr3_save_and_set_training_windows()
1166 /* Save XBAR Windows 4-19 init configurations */ in ddr3_save_and_set_training_windows()
1170 /* Open XBAR Windows 4-7 or 16-19 for other CS */ in ddr3_save_and_set_training_windows()
1217 /* Switching CPU to MRVL ID */ in mv_ddr_pre_training_soc_config()
1249 printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type); in mv_ddr_pre_training_soc_config()
1278 /* 0x14a8 - AXI Control Register */ in mv_ddr_pre_training_soc_config()
1282 * Stage 2 - Training Values Setup in mv_ddr_pre_training_soc_config()
1284 /* Set X-BAR windows for the training sequence */ in mv_ddr_pre_training_soc_config()
1352 printf("DDR3 init controller - FAILED 0x%x\n", status); in mv_ddr_mc_config()
1356 printf("DDR3 init_sequence - FAILED 0x%x\n", status); in mv_ddr_mc_config()
1411 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_configure_phy()
1413 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_configure_phy()
1418 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, phy_id); in ddr3_tip_configure_phy()