47 	u8 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM];  in ddr3_tip_dynamic_read_leveling()  local
56 				rl_values[effective_cs][bus_num][if_id] = 0;  in ddr3_tip_dynamic_read_leveling()
225 					rl_values[effective_cs][bus_num]  in ddr3_tip_dynamic_read_leveling()
274 				data = rl_values[effective_cs][bus_num][if_id];  in ddr3_tip_dynamic_read_leveling()
1687 	u32 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } };  in mv_ddr_rl_dqs_burst()  local
1802 						rl_values[effective_cs][subphy_id][if_id] = i;  in mv_ddr_rl_dqs_burst()
1831 							rl_values[effective_cs][subphy_id][if_id] =  in mv_ddr_rl_dqs_burst()
1832 								(i + rl_values[effective_cs][subphy_id][if_id]) / 2;  in mv_ddr_rl_dqs_burst()
1837 							    rl_values[effective_cs][subphy_id][if_id])  in mv_ddr_rl_dqs_burst()
1839 									rl_values[effective_cs][subphy_id][if_id];  in mv_ddr_rl_dqs_burst()
1841 							    rl_values[effective_cs][subphy_id][if_id])  in mv_ddr_rl_dqs_burst()
1843 									rl_values[effective_cs][subphy_id][if_id];  in mv_ddr_rl_dqs_burst()
1849 						if ((i - rl_values[effective_cs][subphy_id][if_id]) <  in mv_ddr_rl_dqs_burst()
1858 							rl_values[effective_cs][subphy_id][if_id] =  in mv_ddr_rl_dqs_burst()
1859 								(i + rl_values[effective_cs][subphy_id][if_id]) / 2;  in mv_ddr_rl_dqs_burst()
1863 									rl_values[effective_cs][subphy_id][if_id]));  in mv_ddr_rl_dqs_burst()
1868 							    rl_values[effective_cs][subphy_id][if_id])  in mv_ddr_rl_dqs_burst()
1870 									rl_values[effective_cs][subphy_id][if_id];  in mv_ddr_rl_dqs_burst()
1872 							    rl_values[effective_cs][subphy_id][if_id])  in mv_ddr_rl_dqs_burst()
1874 									rl_values[effective_cs][subphy_id][if_id];  in mv_ddr_rl_dqs_burst()
1931 			i = rl_values[effective_cs][subphy_id][if_id] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE);  in mv_ddr_rl_dqs_burst()