26 					      u32 bus_id);
27 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id,
1177 	u32 if_id, bus_id, data, data_tmp;  in ddr3_tip_dynamic_write_leveling_supp()  local
1186 		for (bus_id = 0; bus_id < octets_per_if_num; bus_id++) {  in ddr3_tip_dynamic_write_leveling_supp()
1187 			VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);  in ddr3_tip_dynamic_write_leveling_supp()
1188 			wr_supp_res[if_id][bus_id].is_pup_fail = 1;  in ddr3_tip_dynamic_write_leveling_supp()
1191 				      bus_id, DDR_PHY_DATA,  in ddr3_tip_dynamic_write_leveling_supp()
1199 			    (dev_num, if_id, bus_id) == MV_OK) {  in ddr3_tip_dynamic_write_leveling_supp()
1203 					 if_id, bus_id));  in ddr3_tip_dynamic_write_leveling_supp()
1211 				      ACCESS_TYPE_UNICAST, bus_id, DDR_PHY_DATA,  in ddr3_tip_dynamic_write_leveling_supp()
1216 				      bus_id, DDR_PHY_DATA,  in ddr3_tip_dynamic_write_leveling_supp()
1225 			    (dev_num, if_id, bus_id) == MV_OK) {  in ddr3_tip_dynamic_write_leveling_supp()
1229 					 if_id, bus_id, adll_offset));  in ddr3_tip_dynamic_write_leveling_supp()
1237 				      ACCESS_TYPE_UNICAST, bus_id, DDR_PHY_DATA,  in ddr3_tip_dynamic_write_leveling_supp()
1242 				      bus_id, DDR_PHY_DATA,  in ddr3_tip_dynamic_write_leveling_supp()
1250 			    (dev_num, if_id, bus_id) == MV_OK) {  in ddr3_tip_dynamic_write_leveling_supp()
1254 					 if_id, bus_id, adll_offset));  in ddr3_tip_dynamic_write_leveling_supp()
1260 					 if_id, bus_id));  in ddr3_tip_dynamic_write_leveling_supp()
1288 					      u32 bus_id)  in ddr3_tip_wl_supp_align_phase_shift()  argument
1293 	wr_supp_res[if_id][bus_id].stage = PHASE_SHIFT;  in ddr3_tip_wl_supp_align_phase_shift()
1295 	    (dev_num, if_id, bus_id, 0) == MV_OK)  in ddr3_tip_wl_supp_align_phase_shift()
1300 		     (dev_num, if_id, ACCESS_TYPE_UNICAST, bus_id,  in ddr3_tip_wl_supp_align_phase_shift()
1312 				   ACCESS_TYPE_UNICAST, bus_id, DDR_PHY_DATA,  in ddr3_tip_wl_supp_align_phase_shift()
1315 		    (dev_num, if_id, bus_id, -2) == MV_OK)  in ddr3_tip_wl_supp_align_phase_shift()
1324 				   ACCESS_TYPE_UNICAST, bus_id, DDR_PHY_DATA,  in ddr3_tip_wl_supp_align_phase_shift()
1327 		    (dev_num, if_id, bus_id, 2) == MV_OK)  in ddr3_tip_wl_supp_align_phase_shift()
1336 				   ACCESS_TYPE_UNICAST, bus_id, DDR_PHY_DATA,  in ddr3_tip_wl_supp_align_phase_shift()
1339 		    (dev_num, if_id, bus_id, 4) == MV_OK)  in ddr3_tip_wl_supp_align_phase_shift()
1348 				   ACCESS_TYPE_UNICAST, bus_id, DDR_PHY_DATA,  in ddr3_tip_wl_supp_align_phase_shift()
1351 		    (dev_num, if_id, bus_id, 6) == MV_OK)  in ddr3_tip_wl_supp_align_phase_shift()
1357 			   ACCESS_TYPE_UNICAST, bus_id, DDR_PHY_DATA,  in ddr3_tip_wl_supp_align_phase_shift()
1359 	wr_supp_res[if_id][bus_id].is_pup_fail = 1;  in ddr3_tip_wl_supp_align_phase_shift()
1367 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id,  in ddr3_tip_xsb_compare_test()  argument
1398 		 effective_cs, if_id, bus_id,  in ddr3_tip_xsb_compare_test()
1413 		if ((read_pattern[word_in_pattern] & pup_mask_table[bus_id]) ==  in ddr3_tip_xsb_compare_test()
1415 		     pup_mask_table[bus_id]))  in ddr3_tip_xsb_compare_test()
1421 		wr_supp_res[if_id][bus_id].stage = edge_offset;  in ddr3_tip_xsb_compare_test()
1424 				edge_offset, if_id, bus_id));  in ddr3_tip_xsb_compare_test()
1425 		wr_supp_res[if_id][bus_id].is_pup_fail = 0;  in ddr3_tip_xsb_compare_test()
1432 			 effective_cs, if_id, bus_id, num_of_succ_byte_compare));  in ddr3_tip_xsb_compare_test()
1462 	u32 bus_id, dq_id;  in ddr3_tip_dynamic_write_leveling_seq()  local
1502 	for (bus_id = 0; bus_id < octets_per_if_num; bus_id++) {  in ddr3_tip_dynamic_write_leveling_seq()
1505 			      mask_results_pup_reg_map[bus_id], 0x1 << 24,  in ddr3_tip_dynamic_write_leveling_seq()
1510 	for (bus_id = 0; bus_id < octets_per_if_num; bus_id++) {  in ddr3_tip_dynamic_write_leveling_seq()
1511 		VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);  in ddr3_tip_dynamic_write_leveling_seq()
1514 			      mask_results_pup_reg_map[bus_id], 0, 0x1 << 24));  in ddr3_tip_dynamic_write_leveling_seq()
1529 	u32 bus_id, dq_id;  in ddr3_tip_dynamic_read_leveling_seq()  local
1544 	for (bus_id = 0; bus_id < octets_per_if_num; bus_id++) {  in ddr3_tip_dynamic_read_leveling_seq()
1547 			      mask_results_pup_reg_map[bus_id], 0x1 << 24,  in ddr3_tip_dynamic_read_leveling_seq()
1552 	for (bus_id = 0; bus_id < octets_per_if_num; bus_id++) {  in ddr3_tip_dynamic_read_leveling_seq()
1553 		VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);  in ddr3_tip_dynamic_read_leveling_seq()
1556 			      mask_results_pup_reg_map[bus_id], 0, 0x1 << 24));  in ddr3_tip_dynamic_read_leveling_seq()
1567 	u32 bus_id, dq_id;  in ddr3_tip_dynamic_per_bit_read_leveling_seq()  local
1582 	for (bus_id = 0; bus_id < octets_per_if_num; bus_id++) {  in ddr3_tip_dynamic_per_bit_read_leveling_seq()
1585 			      mask_results_pup_reg_map[bus_id], 0x1 << 24,  in ddr3_tip_dynamic_per_bit_read_leveling_seq()
1606 	u32 bus_id = 0, if_id = 0;  in ddr3_tip_print_wl_supp_result()  local
1615 		for (bus_id = 0; bus_id < octets_per_if_num;  in ddr3_tip_print_wl_supp_result()
1616 		     bus_id++) {  in ddr3_tip_print_wl_supp_result()
1617 			VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);  in ddr3_tip_print_wl_supp_result()
1620 					[bus_id].is_pup_fail));  in ddr3_tip_print_wl_supp_result()
1629 		for (bus_id = 0; bus_id < octets_per_if_num;  in ddr3_tip_print_wl_supp_result()
1630 		     bus_id++) {  in ddr3_tip_print_wl_supp_result()
1631 			VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);  in ddr3_tip_print_wl_supp_result()
1634 					[bus_id].stage));  in ddr3_tip_print_wl_supp_result()