Lines Matching full:enum
43 enum mr_number {
57 enum hws_wl_supp stage;
62 enum mv_ddr_freq frequency,
65 enum mv_ddr_freq frequency,
67 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
69 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
72 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
75 enum hws_access_type access_type,
77 enum hws_ddr_phy phy_type,
79 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access,
80 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
82 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access,
83 u32 if_id, enum hws_access_type e_phy_access, u32 phy_id,
84 enum hws_ddr_phy e_phy_type, u32 reg_addr,
86 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id,
87 enum mv_ddr_freq memory_freq);
103 int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
104 u32 if_id, enum hws_pattern pattern,
106 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern e_pattern);
107 int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
108 u32 if_id, enum hws_dir direction, u32 tx_phases,
112 int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask…