16 u32 phy_reg_bk[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
18 u32 training_res[MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS *
321 		[MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS * search +  in ddr3_tip_get_buf_ptr()
322 		 interface_num * MAX_BUS_NUM * BUS_WIDTH_IN_BITS];  in ddr3_tip_get_buf_ptr()
494 	mask_dq_num_of_regs = octets_per_if_num * BUS_WIDTH_IN_BITS;  in ddr3_tip_ip_training()
654 	for (i = 0; i < BUS_WIDTH_IN_BITS; i++) {  in ddr3_tip_process_result()
665 		for (i = 0; i < BUS_WIDTH_IN_BITS; i++) {  in ddr3_tip_process_result()
763 				start_reg = pup_cnt * BUS_WIDTH_IN_BITS;  in ddr3_tip_read_training_result()
764 				end_reg = (pup_cnt + 1) * BUS_WIDTH_IN_BITS - 1;  in ddr3_tip_read_training_result()
767 					pup_cnt * BUS_WIDTH_IN_BITS + bit_num;  in ddr3_tip_read_training_result()
768 				end_reg = pup_cnt * BUS_WIDTH_IN_BITS + bit_num;  in ddr3_tip_read_training_result()
1113 	u8 bit_state[MAX_BUS_NUM * BUS_WIDTH_IN_BITS] = {0};  in ddr3_tip_ip_training_wrapper()
1114 	u8 h2l_adll_value[MAX_BUS_NUM][BUS_WIDTH_IN_BITS];  in ddr3_tip_ip_training_wrapper()
1115 	u8 l2h_adll_value[MAX_BUS_NUM][BUS_WIDTH_IN_BITS];  in ddr3_tip_ip_training_wrapper()
1166 				bit_end = BUS_WIDTH_IN_BITS;  in ddr3_tip_ip_training_wrapper()
1206 						bit_state[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] =  in ddr3_tip_ip_training_wrapper()
1219 							bit_state[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] =  in ddr3_tip_ip_training_wrapper()
1231 							bit_state[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] =  in ddr3_tip_ip_training_wrapper()
1243 							bit_state[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] =  in ddr3_tip_ip_training_wrapper()
1306 							BUS_WIDTH_IN_BITS + bit_id] & PUP_RESULT_EDGE_1_MASK;  in ddr3_tip_ip_training_wrapper()
1342 							BUS_WIDTH_IN_BITS + bit_id] & PUP_RESULT_EDGE_1_MASK;  in ddr3_tip_ip_training_wrapper()
1429 					if (bit_state[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] == BIT_LOW_UI) {  in ddr3_tip_ip_training_wrapper()
1430 						l2h_if_train_res[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] += 64;  in ddr3_tip_ip_training_wrapper()
1431 						h2l_if_train_res[sybphy_id * BUS_WIDTH_IN_BITS + bit_id] += 64;  in ddr3_tip_ip_training_wrapper()