Lines Matching +full:0 +full:xf
10 #define PATTERN_1 0x55555555
11 #define PATTERN_2 0xaaaaaaaa
61 0xffff
72 0xffff
114 {0x7, 0x7, 2, 0x7, 0x00000, 8}, /* PATTERN_PBS1 */
115 {0x7, 0x7, 2, 0x7, 0x00080, 8}, /* PATTERN_PBS2 */
116 {0x7, 0x7, 2, 0x7, 0x00100, 8}, /* PATTERN_PBS3 */
117 {0x7, 0x7, 2, 0x7, 0x00030, 8}, /* PATTERN_TEST */
118 {0x7, 0x7, 2, 0x7, 0x00100, 8}, /* PATTERN_RL */
119 {0x7, 0x7, 2, 0x7, 0x00100, 8}, /* PATTERN_RL2 */
120 {0x1f, 0xf, 2, 0xf, 0x00680, 32}, /* PATTERN_STATIC_PBS */
121 {0x1f, 0xf, 2, 0xf, 0x00a80, 32}, /* PATTERN_KILLER_DQ0 */
122 {0x1f, 0xf, 2, 0xf, 0x01280, 32}, /* PATTERN_KILLER_DQ1 */
123 {0x1f, 0xf, 2, 0xf, 0x01a80, 32}, /* PATTERN_KILLER_DQ2 */
124 {0x1f, 0xf, 2, 0xf, 0x02280, 32}, /* PATTERN_KILLER_DQ3 */
125 {0x1f, 0xf, 2, 0xf, 0x02a80, 32}, /* PATTERN_KILLER_DQ4 */
126 {0x1f, 0xf, 2, 0xf, 0x03280, 32}, /* PATTERN_KILLER_DQ5 */
127 {0x1f, 0xf, 2, 0xf, 0x03a80, 32}, /* PATTERN_KILLER_DQ6 */
128 {0x1f, 0xf, 2, 0xf, 0x04280, 32}, /* PATTERN_KILLER_DQ7 */
129 {0x1f, 0xf, 2, 0xf, 0x00e80, 32}, /* PATTERN_KILLER_DQ0_64 */
130 {0x1f, 0xf, 2, 0xf, 0x01680, 32}, /* PATTERN_KILLER_DQ1_64 */
131 {0x1f, 0xf, 2, 0xf, 0x01e80, 32}, /* PATTERN_KILLER_DQ2_64 */
132 {0x1f, 0xf, 2, 0xf, 0x02680, 32}, /* PATTERN_KILLER_DQ3_64 */
133 {0x1f, 0xf, 2, 0xf, 0x02e80, 32}, /* PATTERN_KILLER_DQ4_64 */
134 {0x1f, 0xf, 2, 0xf, 0x03680, 32}, /* PATTERN_KILLER_DQ5_64 */
135 {0x1f, 0xf, 2, 0xf, 0x03e80, 32}, /* PATTERN_KILLER_DQ6_64 */
136 {0x1f, 0xf, 2, 0xf, 0x04680, 32}, /* PATTERN_KILLER_DQ7_64 */
137 {0x1f, 0xf, 2, 0xf, 0x04a80, 32}, /* PATTERN_KILLER_DQ0_INV */
138 {0x1f, 0xf, 2, 0xf, 0x05280, 32}, /* PATTERN_KILLER_DQ1_INV */
139 {0x1f, 0xf, 2, 0xf, 0x05a80, 32}, /* PATTERN_KILLER_DQ2_INV */
140 {0x1f, 0xf, 2, 0xf, 0x06280, 32}, /* PATTERN_KILLER_DQ3_INV */
141 {0x1f, 0xf, 2, 0xf, 0x06a80, 32}, /* PATTERN_KILLER_DQ4_INV */
142 {0x1f, 0xf, 2, 0xf, 0x07280, 32}, /* PATTERN_KILLER_DQ5_INV */
143 {0x1f, 0xf, 2, 0xf, 0x07a80, 32}, /* PATTERN_KILLER_DQ6_INV */
144 {0x1f, 0xf, 2, 0xf, 0x08280, 32}, /* PATTERN_KILLER_DQ7_INV */
145 {0x1f, 0xf, 2, 0xf, 0x04e80, 32}, /* PATTERN_KILLER_DQ0_INV_64 */
146 {0x1f, 0xf, 2, 0xf, 0x05680, 32}, /* PATTERN_KILLER_DQ1_INV_64 */
147 {0x1f, 0xf, 2, 0xf, 0x05e80, 32}, /* PATTERN_KILLER_DQ2_INV_64 */
148 {0x1f, 0xf, 2, 0xf, 0x06680, 32}, /* PATTERN_KILLER_DQ3_INV_64 */
149 {0x1f, 0xf, 2, 0xf, 0x06e80, 32}, /* PATTERN_KILLER_DQ4_INV_64 */
150 {0x1f, 0xf, 2, 0xf, 0x07680, 32}, /* PATTERN_KILLER_DQ5_INV_64 */
151 {0x1f, 0xf, 2, 0xf, 0x07e80, 32}, /* PATTERN_KILLER_DQ6_INV_64 */
152 {0x1f, 0xf, 2, 0xf, 0x08680, 32}, /* PATTERN_KILLER_DQ7_INV_64 */
153 {0x1f, 0xf, 2, 0xf, 0x08a80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ0 */
154 {0x1f, 0xf, 2, 0xf, 0x09280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ1 */
155 {0x1f, 0xf, 2, 0xf, 0x09a80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ2 */
156 {0x1f, 0xf, 2, 0xf, 0x0a280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ3 */
157 {0x1f, 0xf, 2, 0xf, 0x0aa80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ4 */
158 {0x1f, 0xf, 2, 0xf, 0x0b280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ5 */
159 {0x1f, 0xf, 2, 0xf, 0x0ba80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ6 */
160 {0x1f, 0xf, 2, 0xf, 0x0c280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ7 */
161 {0x1f, 0xf, 2, 0xf, 0x08e80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ0_64 */
162 {0x1f, 0xf, 2, 0xf, 0x09680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ1_64 */
163 {0x1f, 0xf, 2, 0xf, 0x09e80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ2_64 */
164 {0x1f, 0xf, 2, 0xf, 0x0a680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ3_64 */
165 {0x1f, 0xf, 2, 0xf, 0x0ae80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ4_64 */
166 {0x1f, 0xf, 2, 0xf, 0x0b680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ5_64 */
167 {0x1f, 0xf, 2, 0xf, 0x0be80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ6_64 */
168 {0x1f, 0xf, 2, 0xf, 0x0c680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ7_64 */
169 {0x1f, 0xf, 2, 0xf, 0x0ca80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ0 */
170 {0x1f, 0xf, 2, 0xf, 0x0d280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ1 */
171 {0x1f, 0xf, 2, 0xf, 0x0da80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ2 */
172 {0x1f, 0xf, 2, 0xf, 0x0e280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ3 */
173 {0x1f, 0xf, 2, 0xf, 0x0ea80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ4 */
174 {0x1f, 0xf, 2, 0xf, 0x0f280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ5 */
175 {0x1f, 0xf, 2, 0xf, 0x0fa80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ6 */
176 {0x1f, 0xf, 2, 0xf, 0x10280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ7 */
177 {0x1f, 0xf, 2, 0xf, 0x0ce80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ0_64 */
178 {0x1f, 0xf, 2, 0xf, 0x0d680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ1_64 */
179 {0x1f, 0xf, 2, 0xf, 0x0de80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ2_64 */
180 {0x1f, 0xf, 2, 0xf, 0x0e680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ3_64 */
181 {0x1f, 0xf, 2, 0xf, 0x0ee80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ4_64 */
182 {0x1f, 0xf, 2, 0xf, 0x0f680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ5_64 */
183 {0x1f, 0xf, 2, 0xf, 0x0fe80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ6_64 */
184 {0x1f, 0xf, 2, 0xf, 0x10680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ7_64 */
185 {0x1f, 0xf, 2, 0xf, 0x10a80, 32}, /* PATTERN_ISI_XTALK_FREE */
186 {0x1f, 0xf, 2, 0xf, 0x10e80, 32}, /* PATTERN_ISI_XTALK_FREE_64 */
187 {0x1f, 0xf, 2, 0xf, 0x11280, 32}, /* PATTERN_VREF */
188 {0x1f, 0xf, 2, 0xf, 0x11680, 32}, /* PATTERN_VREF_64 */
189 {0x1f, 0xf, 2, 0xf, 0x11a80, 32}, /* PATTERN_VREF_INV */
190 {0x1f, 0xf, 2, 0xf, 0x11e80, 32}, /* PATTERN_FULL_SSO_0T */
191 {0x1f, 0xf, 2, 0xf, 0x12280, 32}, /* PATTERN_FULL_SSO_1T */
192 {0x1f, 0xf, 2, 0xf, 0x12680, 32}, /* PATTERN_FULL_SSO_2T */
193 {0x1f, 0xf, 2, 0xf, 0x12a80, 32}, /* PATTERN_FULL_SSO_3T */
194 {0x1f, 0xf, 2, 0xf, 0x12e80, 32}, /* PATTERN_RESONANCE_1T */
195 {0x1f, 0xf, 2, 0xf, 0x13280, 32}, /* PATTERN_RESONANCE_2T */
196 {0x1f, 0xf, 2, 0xf, 0x13680, 32}, /* PATTERN_RESONANCE_3T */
197 {0x1f, 0xf, 2, 0xf, 0x13a80, 32}, /* PATTERN_RESONANCE_4T */
198 {0x1f, 0xf, 2, 0xf, 0x13e80, 32}, /* PATTERN_RESONANCE_5T */
199 {0x1f, 0xf, 2, 0xf, 0x14280, 32}, /* PATTERN_RESONANCE_6T */
200 {0x1f, 0xf, 2, 0xf, 0x14680, 32}, /* PATTERN_RESONANCE_7T */
201 {0x1f, 0xf, 2, 0xf, 0x14a80, 32}, /* PATTERN_RESONANCE_8T */
202 {0x1f, 0xf, 2, 0xf, 0x14e80, 32}, /* PATTERN_RESONANCE_9T */
203 {0x1f, 0xf, 2, 0xf, 0x15280, 32}, /* PATTERN_ZERO */
204 {0x1f, 0xf, 2, 0xf, 0x15680, 32} /* PATTERN_ONE */
213 {1, 1, 2, 1, 0x0080, 2}, /* PATTERN_PBS1 */
214 {1, 1, 2, 1, 0x00c0, 2}, /* PATTERN_PBS2 */
215 {1, 1, 2, 1, 0x0380, 2}, /* PATTERN_PBS3 */
216 {1, 1, 2, 1, 0x0040, 2}, /* PATTERN_TEST */
217 {1, 1, 2, 1, 0x0100, 2}, /* PATTERN_RL */
218 {1, 1, 2, 1, 0x0000, 2}, /* PATTERN_RL2 */
219 {0xf, 0x7, 2, 0x7, 0x0140, 16}, /* PATTERN_STATIC_PBS */
220 {0xf, 0x7, 2, 0x7, 0x0190, 16}, /* PATTERN_KILLER_DQ0 */
221 {0xf, 0x7, 2, 0x7, 0x01d0, 16}, /* PATTERN_KILLER_DQ1 */
222 {0xf, 0x7, 2, 0x7, 0x0210, 16}, /* PATTERN_KILLER_DQ2 */
223 {0xf, 0x7, 2, 0x7, 0x0250, 16}, /* PATTERN_KILLER_DQ3 */
224 {0xf, 0x7, 2, 0x7, 0x0290, 16}, /* PATTERN_KILLER_DQ4 */
225 {0xf, 0x7, 2, 0x7, 0x02d0, 16}, /* PATTERN_KILLER_DQ5 */
226 {0xf, 0x7, 2, 0x7, 0x0310, 16}, /* PATTERN_KILLER_DQ6 */
227 {0xf, 0x7, 2, 0x7, 0x0350, 16}, /* PATTERN_KILLER_DQ7 */
228 {0xf, 0x7, 2, 0x7, 0x04c0, 16}, /* PATTERN_VREF */
229 {0xf, 0x7, 2, 0x7, 0x03c0, 16}, /* PATTERN_FULL_SSO_1T */
230 {0xf, 0x7, 2, 0x7, 0x0400, 16}, /* PATTERN_FULL_SSO_2T */
231 {0xf, 0x7, 2, 0x7, 0x0440, 16}, /* PATTERN_FULL_SSO_3T */
232 {0xf, 0x7, 2, 0x7, 0x0480, 16}, /* PATTERN_FULL_SSO_4T */
233 {0xf, 7, 2, 7, 0x6280, 16}, /* PATTERN_SSO_FULL_XTALK_DQ1 */
234 {0xf, 7, 2, 7, 0x6680, 16}, /* PATTERN_SSO_FULL_XTALK_DQ1 */
235 {0xf, 7, 2, 7, 0x6A80, 16}, /* PATTERN_SSO_FULL_XTALK_DQ2 */
236 {0xf, 7, 2, 7, 0x6E80, 16}, /* PATTERN_SSO_FULL_XTALK_DQ3 */
237 {0xf, 7, 2, 7, 0x7280, 16}, /* PATTERN_SSO_FULL_XTALK_DQ4 */
238 {0xf, 7, 2, 7, 0x7680, 16}, /* PATTERN_SSO_FULL_XTALK_DQ5 */
239 {0xf, 7, 2, 7, 0x7A80, 16}, /* PATTERN_SSO_FULL_XTALK_DQ6 */
240 {0xf, 7, 2, 7, 0x7E80, 16}, /* PATTERN_SSO_FULL_XTALK_DQ7 */
241 {0xf, 7, 2, 7, 0x8280, 16}, /* PATTERN_SSO_XTALK_FREE_DQ0 */
242 {0xf, 7, 2, 7, 0x8680, 16}, /* PATTERN_SSO_XTALK_FREE_DQ1 */
243 {0xf, 7, 2, 7, 0x8A80, 16}, /* PATTERN_SSO_XTALK_FREE_DQ2 */
244 {0xf, 7, 2, 7, 0x8E80, 16}, /* PATTERN_SSO_XTALK_FREE_DQ3 */
245 {0xf, 7, 2, 7, 0x9280, 16}, /* PATTERN_SSO_XTALK_FREE_DQ4 */
246 {0xf, 7, 2, 7, 0x9680, 16}, /* PATTERN_SSO_XTALK_FREE_DQ5 */
247 {0xf, 7, 2, 7, 0x9A80, 16}, /* PATTERN_SSO_XTALK_FREE_DQ6 */
248 {0xf, 7, 2, 7, 0x9E80, 16}, /* PATTERN_SSO_XTALK_FREE_DQ7 */
249 {0xf, 7, 2, 7, 0xA280, 16} /* PATTERN_ISI_XTALK_FREE */
258 {3, 3, 2, 3, 0x0080, 4}, /* PATTERN_PBS1 */
259 {3, 3, 2, 3, 0x00c0, 4}, /* PATTERN_PBS2 */
260 {3, 3, 2, 3, 0x0380, 4}, /* PATTERN_PBS3 */
261 {3, 3, 2, 3, 0x0040, 4}, /* PATTERN_TEST */
262 {3, 3, 2, 3, 0x0100, 4}, /* PATTERN_RL */
263 {3, 3, 2, 3, 0x0000, 4}, /* PATTERN_RL2 */
264 {0x1f, 0xf, 2, 0xf, 0x0140, 32}, /* PATTERN_STATIC_PBS */
265 {0x1f, 0xf, 2, 0xf, 0x0190, 32}, /* PATTERN_KILLER_DQ0 */
266 {0x1f, 0xf, 2, 0xf, 0x01d0, 32}, /* PATTERN_KILLER_DQ1 */
267 {0x1f, 0xf, 2, 0xf, 0x0210, 32}, /* PATTERN_KILLER_DQ2 */
268 {0x1f, 0xf, 2, 0xf, 0x0250, 32}, /* PATTERN_KILLER_DQ3 */
269 {0x1f, 0xf, 2, 0xf, 0x0290, 32}, /* PATTERN_KILLER_DQ4 */
270 {0x1f, 0xf, 2, 0xf, 0x02d0, 32}, /* PATTERN_KILLER_DQ5 */
271 {0x1f, 0xf, 2, 0xf, 0x0310, 32}, /* PATTERN_KILLER_DQ6 */
272 {0x1f, 0xf, 2, 0xf, 0x0350, 32}, /* PATTERN_KILLER_DQ7 */
273 {0x1f, 0xf, 2, 0xf, 0x04c0, 32}, /* PATTERN_VREF */
274 {0x1f, 0xf, 2, 0xf, 0x03c0, 32}, /* PATTERN_FULL_SSO_1T */
275 {0x1f, 0xf, 2, 0xf, 0x0400, 32}, /* PATTERN_FULL_SSO_2T */
276 {0x1f, 0xf, 2, 0xf, 0x0440, 32}, /* PATTERN_FULL_SSO_3T */
277 {0x1f, 0xf, 2, 0xf, 0x0480, 32}, /* PATTERN_FULL_SSO_4T */
278 {0x1f, 0xF, 2, 0xf, 0x6280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ0 */
279 {0x1f, 0xF, 2, 0xf, 0x6680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ1 */
280 {0x1f, 0xF, 2, 0xf, 0x6A80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ2 */
281 {0x1f, 0xF, 2, 0xf, 0x6E80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ3 */
282 {0x1f, 0xF, 2, 0xf, 0x7280, 32}, /* PATTERN_SSO_FULL_XTALK_DQ4 */
283 {0x1f, 0xF, 2, 0xf, 0x7680, 32}, /* PATTERN_SSO_FULL_XTALK_DQ5 */
284 {0x1f, 0xF, 2, 0xf, 0x7A80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ6 */
285 {0x1f, 0xF, 2, 0xf, 0x7E80, 32}, /* PATTERN_SSO_FULL_XTALK_DQ7 */
286 {0x1f, 0xF, 2, 0xf, 0x8280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ0 */
287 {0x1f, 0xF, 2, 0xf, 0x8680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ1 */
288 {0x1f, 0xF, 2, 0xf, 0x8A80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ2 */
289 {0x1f, 0xF, 2, 0xf, 0x8E80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ3 */
290 {0x1f, 0xF, 2, 0xf, 0x9280, 32}, /* PATTERN_SSO_XTALK_FREE_DQ4 */
291 {0x1f, 0xF, 2, 0xf, 0x9680, 32}, /* PATTERN_SSO_XTALK_FREE_DQ5 */
292 {0x1f, 0xF, 2, 0xf, 0x9A80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ6 */
293 {0x1f, 0xF, 2, 0xf, 0x9E80, 32}, /* PATTERN_SSO_XTALK_FREE_DQ7 */
294 {0x1f, 0xF, 2, 0xf, 0xA280, 32} /* PATTERN_ISI_XTALK_FREE */
385 (0x3 | (effective_cs << 26)), 0xc000003)); in ddr3_tip_ip_training()
389 DUAL_DUNIT_CFG_REG, 0, 1 << 3)); in ddr3_tip_ip_training()
393 ODPG_DATA_CTRL_REG, 0x3 | cs_num << 26, in ddr3_tip_ip_training()
394 0x3 | 3 << 26)); in ddr3_tip_ip_training()
402 pattern_table[pattern].tx_burst_size : 0; in ddr3_tip_ip_training()
403 delay_between_burst = (direction == OPER_WRITE) ? 2 : 0; in ddr3_tip_ip_training()
404 rd_mode = (direction == OPER_WRITE) ? 1 : 0; in ddr3_tip_ip_training()
411 reg_data = (direction == OPER_READ) ? 0 : (0x3 << 30); in ddr3_tip_ip_training()
412 reg_data |= (direction == OPER_READ) ? 0x60 : 0xfa; in ddr3_tip_ip_training()
417 reg_data = (edge_comp == EDGE_PF || edge_comp == EDGE_FP) ? 0 : 1 << 6; in ddr3_tip_ip_training()
419 (1 << 7) : 0; in ddr3_tip_ip_training()
423 reg_data |= 0xe << 14; in ddr3_tip_ip_training()
429 reg_data |= (0 << 20); in ddr3_tip_ip_training()
431 reg_data |= (0 << 20); in ddr3_tip_ip_training()
439 reg_data | (0x7 << 8) | (0x7 << 11), in ddr3_tip_ip_training()
440 (0x3 | (0x3 << 2) | (0x3 << 6) | (1 << 5) | (0x7 << 8) | in ddr3_tip_ip_training()
441 (0x7 << 11) | (0xf << 14) | (0x3 << 18) | (3 << 20)))); in ddr3_tip_ip_training()
442 reg_data = (search_dir == HWS_LOW2HIGH) ? 0 : (1 << 8); in ddr3_tip_ip_training()
446 0xff | (1 << 8) | (0xffff << 9) | (1 << 25) | (1 << 26))); in ddr3_tip_ip_training()
449 * Write2_dunit(0x10b4, Number_iteration , [15:0]) in ddr3_tip_ip_training()
454 0xffff)); in ddr3_tip_ip_training()
458 * Write2_dunit(0x10c0, 0x5f , [7:0]) in ddr3_tip_ip_training()
468 * LOOP 0x00000001 + 4*n: in ddr3_tip_ip_training()
469 * where n (0-3) represents M_CS number in ddr3_tip_ip_training()
472 * Write2_dunit(0x10c0, 0x1 , [7:0]) in ddr3_tip_ip_training()
482 /* TBD not defined in 0.5.0 requirement */ in ddr3_tip_ip_training()
485 /* TBD not defined in 0.5.0 requirement */ in ddr3_tip_ip_training()
488 reg_data |= (0x6 << 28); in ddr3_tip_ip_training()
492 0xff | (0xffff << 8) | (0xf << 24) | (u32) (0xf << 28))); in ddr3_tip_ip_training()
498 for (index_cnt = 0; index_cnt < mask_dq_num_of_regs; in ddr3_tip_ip_training()
502 mask_results_dq_reg_map[index_cnt], 0, in ddr3_tip_ip_training()
507 for (pup_id = 0; pup_id < octets_per_if_num; in ddr3_tip_ip_training()
521 for (index_cnt = 0; index_cnt < mask_pup_num_of_regs; in ddr3_tip_ip_training()
530 for (index_cnt = 0; index_cnt < mask_pup_num_of_regs; in ddr3_tip_ip_training()
534 mask_results_pup_reg_map[index_cnt], 0, in ddr3_tip_ip_training()
537 for (index_cnt = 0; index_cnt < mask_dq_num_of_regs; in ddr3_tip_ip_training()
554 train_status[0] = HWS_TRAINING_IP_STATUS_TIMEOUT; in ddr3_tip_ip_training()
557 train_status[0] = HWS_TRAINING_IP_STATUS_SUCCESS; in ddr3_tip_ip_training()
559 train_status[0] = HWS_TRAINING_IP_STATUS_FAIL; in ddr3_tip_ip_training()
562 ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_ip_training()
563 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS); in ddr3_tip_ip_training()
575 u32 pattern_length_cnt = 0; in ddr3_tip_load_pattern_to_odpg()
579 for (pattern_length_cnt = 0; in ddr3_tip_load_pattern_to_odpg()
631 u32 data_value = 0; in ddr3_tip_configure_odpg()
639 ODPG_DATA_CTRL_REG, data_value, 0xaffffffc); in ddr3_tip_configure_odpg()
654 for (i = 0; i < BUS_WIDTH_IN_BITS; i++) { in ddr3_tip_process_result()
656 if (res == 0) { in ddr3_tip_process_result()
657 lock_success = 0; in ddr3_tip_process_result()
665 for (i = 0; i < BUS_WIDTH_IN_BITS; i++) { in ddr3_tip_process_result()
677 ("i %d ar_result[i] 0x%x tap_val %d max_val %d min_val %d Edge_result %d\n", in ddr3_tip_process_result()
719 (cs_num_type == 0) ? 1 << 3 : 0, (1 << 3))); in ddr3_tip_read_training_result()
751 start_pup = 0; in ddr3_tip_read_training_result()
792 if (is_read_from_db == 0) { in ddr3_tip_read_training_result()
802 TIP_ENG_LOCK) == 0) { in ddr3_tip_read_training_result()
821 ("reg_offset %d value 0x%x addr %p\n", in ddr3_tip_read_training_result()
849 u32 pattern = 0, if_id; in ddr3_tip_load_all_pattern_to_mem()
852 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_all_pattern_to_mem()
857 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_all_pattern_to_mem()
865 for (pattern = 0; pattern < PATTERN_LAST; pattern++) in ddr3_tip_load_all_pattern_to_mem()
886 0x1 | (pattern_table[pattern].num_of_phases_tx << 5) | in ddr3_tip_load_pattern_to_mem()
889 (pattern_table[pattern].num_of_phases_rx << 21) | (0x1 << 25) | in ddr3_tip_load_pattern_to_mem()
897 ODPG_DATA_CTRL_REG, (0x1 | (effective_cs << 26)), in ddr3_tip_load_pattern_to_mem()
898 0xc000003)); in ddr3_tip_load_pattern_to_mem()
902 ODPG_DATA_WR_DATA_ERR_REG, 0, 0x1)); in ddr3_tip_load_pattern_to_mem()
909 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_load_pattern_to_mem()
915 0x3, 0xf)); in ddr3_tip_load_pattern_to_mem()
922 ODPG_DATA_CTRL_REG, (u32)(0x1 << 31), in ddr3_tip_load_pattern_to_mem()
923 (u32)(0x1 << 31))); in ddr3_tip_load_pattern_to_mem()
933 ODPG_DATA_CTRL_REG, (0x1 << 30), (u32) (0x3 << 30))); in ddr3_tip_load_pattern_to_mem()
938 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_mem()
944 SDRAM_ODT_CTRL_HIGH_REG, 0x0, 0xf)); in ddr3_tip_load_pattern_to_mem()
971 u32 interface_num = 0, start_if, end_if, init_value_used; in ddr3_tip_ip_training_wrapper_int()
974 u8 cons_tap = 0; in ddr3_tip_ip_training_wrapper_int()
1032 start_if = 0; in ddr3_tip_ip_training_wrapper_int()
1042 cs_num = 0; in ddr3_tip_ip_training_wrapper_int()
1048 train_cs_type, NULL, 0, cons_tap, in ddr3_tip_ip_training_wrapper_int()
1049 0)); in ddr3_tip_ip_training_wrapper_int()
1065 * 1. BIT_LOW_UI 0 =< VW =< 31 in case of jitter use: VW_L <= 31, VW_H <= 31
1077 * 2.BYTE_HOMOGENEOUS_LOW 0 =< VW =< 31
1109 u32 bit_id, start_if, end_if, bit_end = 0; in ddr3_tip_ip_training_wrapper()
1110 u32 *result[HWS_SEARCH_DIR_LIMIT] = { 0 }; in ddr3_tip_ip_training_wrapper()
1111 u8 cons_tap = (direction == OPER_WRITE) ? (64) : (0); in ddr3_tip_ip_training_wrapper()
1112 u8 bit_bit_mask[MAX_BUS_NUM] = { 0 }, bit_bit_mask_active = 0; in ddr3_tip_ip_training_wrapper()
1113 u8 bit_state[MAX_BUS_NUM * BUS_WIDTH_IN_BITS] = {0}; in ddr3_tip_ip_training_wrapper()
1150 start_if = 0; in ddr3_tip_ip_training_wrapper()
1160 bit_bit_mask_active = 0; /* clean the flag for level2 search */ in ddr3_tip_ip_training_wrapper()
1161 memset(bit_state, 0, sizeof(bit_state)); in ddr3_tip_ip_training_wrapper()
1163 for (sybphy_id = 0; sybphy_id < octets_per_if_num; sybphy_id++) { in ddr3_tip_ip_training_wrapper()
1168 bit_end = 0; in ddr3_tip_ip_training_wrapper()
1171 bit_bit_mask[sybphy_id] = 0; in ddr3_tip_ip_training_wrapper()
1173 for (bit_id = 0; bit_id < bit_end; bit_id++) { in ddr3_tip_ip_training_wrapper()
1175 l2h_adll_value[sybphy_id][bit_id] = 0; in ddr3_tip_ip_training_wrapper()
1183 &result[search_dir_id], 1, 0, 0); in ddr3_tip_ip_training_wrapper()
1189 e1 = GET_TAP_RESULT(result[HWS_LOW2HIGH][0], EDGE_1); in ddr3_tip_ip_training_wrapper()
1190 e2 = GET_TAP_RESULT(result[HWS_HIGH2LOW][0], EDGE_1); in ddr3_tip_ip_training_wrapper()
1193 ("if_id %d sybphy_id %d bit %d l2h 0x%x (e1 0x%x) h2l 0x%x (e2 0x%x)\n", in ddr3_tip_ip_training_wrapper()
1194 if_id, sybphy_id, bit_id, result[HWS_LOW2HIGH][0], e1, in ddr3_tip_ip_training_wrapper()
1195 result[HWS_HIGH2LOW][0], e2)); in ddr3_tip_ip_training_wrapper()
1197 (GET_LOCK_RESULT(result[HWS_LOW2HIGH][0]) && in ddr3_tip_ip_training_wrapper()
1198 GET_LOCK_RESULT(result[HWS_HIGH2LOW][0])); in ddr3_tip_ip_training_wrapper()
1258 ("if_id %d sybphy_id %d bit %d l2h 0x%x (e1 0x%x)" in ddr3_tip_ip_training_wrapper()
1259 "h2l 0x%x (e2 0x%x): bit cannot be categorized\n", in ddr3_tip_ip_training_wrapper()
1260 if_id, sybphy_id, bit_id, result[HWS_LOW2HIGH][0], e1, in ddr3_tip_ip_training_wrapper()
1261 result[HWS_HIGH2LOW][0], e2)); in ddr3_tip_ip_training_wrapper()
1270 if (bit_bit_mask_active != 0) { in ddr3_tip_ip_training_wrapper()
1284 for (sybphy_id = 0; sybphy_id < octets_per_if_num; sybphy_id++) { in ddr3_tip_ip_training_wrapper()
1287 if (bit_bit_mask[sybphy_id] == 0) in ddr3_tip_ip_training_wrapper()
1290 for (bit_id = 0; bit_id < bit_end; bit_id++) { in ddr3_tip_ip_training_wrapper()
1291 if ((bit_bit_mask[sybphy_id] & (1 << bit_id)) == 0) in ddr3_tip_ip_training_wrapper()
1299 &l2h_if_train_res, 0, 0, 1); in ddr3_tip_ip_training_wrapper()
1321 for (sybphy_id = 0; sybphy_id < octets_per_if_num; sybphy_id++) { in ddr3_tip_ip_training_wrapper()
1324 if (bit_bit_mask[sybphy_id] == 0) in ddr3_tip_ip_training_wrapper()
1327 for (bit_id = 0; bit_id < bit_end; bit_id++) { in ddr3_tip_ip_training_wrapper()
1328 if ((bit_bit_mask[sybphy_id] & (1 << bit_id)) == 0) in ddr3_tip_ip_training_wrapper()
1335 &h2l_if_train_res, 0, cons_tap, 1); in ddr3_tip_ip_training_wrapper()
1351 for (sybphy_id = 0; sybphy_id < octets_per_if_num; sybphy_id++) { in ddr3_tip_ip_training_wrapper()
1356 center_subphy_adll_window[sybphy_id] = 0; in ddr3_tip_ip_training_wrapper()
1357 max_center_subphy_adll[sybphy_id] = 0; in ddr3_tip_ip_training_wrapper()
1360 for (bit_id = 0; bit_id < bit_end; bit_id++) { in ddr3_tip_ip_training_wrapper()
1399 for (sybphy_id = 0; sybphy_id < octets_per_if_num; sybphy_id++) { in ddr3_tip_ip_training_wrapper()
1426 ("if_id %d sybphy_id %d byte state 0x%x\n", in ddr3_tip_ip_training_wrapper()
1428 for (bit_id = 0; bit_id < bit_end; bit_id++) { in ddr3_tip_ip_training_wrapper()
1460 u32 bus_cnt = 0, if_id, dev_num = 0; in ddr3_tip_load_phy_values()
1464 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_phy_values()
1466 for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) { in ddr3_tip_load_phy_values()
1475 [0])); in ddr3_tip_load_phy_values()
1497 [0])); in ddr3_tip_load_phy_values()
1530 u32 search_state = 0; in ddr3_tip_training_ip_test()
1537 for (search_state = 0; search_state < HWS_SEARCH_DIR_LIMIT; in ddr3_tip_training_ip_test()
1540 ACCESS_TYPE_MULTICAST, 0, in ddr3_tip_training_ip_test()
1541 ACCESS_TYPE_MULTICAST, 0, in ddr3_tip_training_ip_test()
1545 0xfff, init_val1, in ddr3_tip_training_ip_test()
1552 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; in ddr3_tip_training_ip_test()
1555 for (pup_id = 0; pup_id < in ddr3_tip_training_ip_test()
1568 CS_SINGLE, &res, 1, 0, in ddr3_tip_training_ip_test()
1569 0)); in ddr3_tip_training_ip_test()
1573 ("search_state %d if_id %d pup_id %d 0x%x\n", in ddr3_tip_training_ip_test()
1575 pup_id, res[0])); in ddr3_tip_training_ip_test()
1579 ("search_state %d if_id %d pup_id %d 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", in ddr3_tip_training_ip_test()
1581 pup_id, res[0], in ddr3_tip_training_ip_test()
1592 ddr3_tip_load_phy_values(0); in ddr3_tip_training_ip_test()
1601 return 0; in mv_ddr_pattern_start_addr_set()
1610 else if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == 0) in ddr3_tip_get_pattern_table()
1641 #define LOW_NIBBLE_BYTE_MASK 0xf
1642 #define HIGH_NIBBLE_BYTE_MASK 0xf0
1648 u32 pattern_len = 0; in mv_ddr_load_dm_pattern_to_odpg()
1652 for (pattern_len = 0; in mv_ddr_load_dm_pattern_to_odpg()
1656 data_low = pattern_table_get_word(0, pattern, (u8)pattern_len); in mv_ddr_load_dm_pattern_to_odpg()
1659 data_low = pattern_table_get_word(0, pattern, (u8)(pattern_len * 2)); in mv_ddr_load_dm_pattern_to_odpg()
1660 data_high = pattern_table_get_word(0, pattern, (u8)(pattern_len * 2 + 1)); in mv_ddr_load_dm_pattern_to_odpg()
1669 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_WR_DATA_LOW_REG, data_low, MASK_ALL_BITS); in mv_ddr_load_dm_pattern_to_odpg()
1670 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_WR_DATA_HIGH_REG, data_high, MASK_ALL_BITS); in mv_ddr_load_dm_pattern_to_odpg()
1671 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_WR_ADDR_REG, in mv_ddr_load_dm_pattern_to_odpg()