Lines Matching refs:pattern_table
31 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); in ddr3_tip_bist_activate() local
48 pattern_table[pattern].tx_burst_size : 0; in ddr3_tip_bist_activate()
52 pattern_table[pattern].num_of_phases_tx, tx_burst_size, in ddr3_tip_bist_activate()
53 pattern_table[pattern].num_of_phases_rx, in ddr3_tip_bist_activate()
446 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); in mv_ddr_odpg_bist_prepare() local
469 tx_burst_size = pattern_table[pattern].tx_burst_size; in mv_ddr_odpg_bist_prepare()
477 ddr3_tip_configure_odpg(0, access_type, 0, dir, pattern_table[pattern].num_of_phases_tx, in mv_ddr_odpg_bist_prepare()
478 tx_burst_size, pattern_table[pattern].num_of_phases_rx, burst_delay, in mv_ddr_odpg_bist_prepare()
489 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); in mv_ddr_dm_vw_get() local
509 bist_offset, cs, pattern_table[pattern].num_of_phases_tx, in mv_ddr_dm_vw_get()
519 pattern_table[pattern].num_of_phases_tx, in mv_ddr_dm_vw_get()
520 pattern_table[pattern].tx_burst_size, in mv_ddr_dm_vw_get()
521 pattern_table[pattern].num_of_phases_rx, in mv_ddr_dm_vw_get()
541 bist_offset, cs, pattern_table[pattern].num_of_phases_tx, in mv_ddr_dm_vw_get()
552 pattern_table[pattern].num_of_phases_tx, in mv_ddr_dm_vw_get()
553 pattern_table[pattern].tx_burst_size, in mv_ddr_dm_vw_get()
554 pattern_table[pattern].num_of_phases_rx, in mv_ddr_dm_vw_get()
585 mv_ddr_pattern_start_addr_set(pattern_table, pattern, odpg_addr); in mv_ddr_dm_vw_get()