20 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,  in ddr3_tip_bist_activate()  argument
44 	ddr3_tip_load_pattern_to_odpg(0, access_type, 0, pattern, offset);  in ddr3_tip_bist_activate()
48 		pattern_table[pattern].tx_burst_size : 0;  in ddr3_tip_bist_activate()
52 		      pattern_table[pattern].num_of_phases_tx, tx_burst_size,  in ddr3_tip_bist_activate()
53 		      pattern_table[pattern].num_of_phases_rx,  in ddr3_tip_bist_activate()
118 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,  in hws_ddr3_run_bist()  argument
130 		ret = ddr3_tip_bist_activate(dev_num, pattern,  in hws_ddr3_run_bist()
141 		ret = ddr3_tip_bist_activate(dev_num, pattern,  in hws_ddr3_run_bist()
224 static int mv_ddr_tip_bist(enum hws_dir dir, u32 val, enum hws_pattern pattern, u32 cs, u32 *result)  in mv_ddr_tip_bist()  argument
234 			     TIP_ITERATION_NUM, pattern, EDGE_FP, CS_SINGLE, cs, &training_result);  in mv_ddr_tip_bist()
441 static int mv_ddr_odpg_bist_prepare(enum hws_pattern pattern, enum hws_access_type access_type,  in mv_ddr_odpg_bist_prepare()  argument
462 	if (pattern == PATTERN_00 || pattern == PATTERN_FF)  in mv_ddr_odpg_bist_prepare()
463 		ddr3_tip_load_pattern_to_odpg(0, access_type, 0, pattern, offset);  in mv_ddr_odpg_bist_prepare()
465 		mv_ddr_load_dm_pattern_to_odpg(access_type, pattern, dm_dir);  in mv_ddr_odpg_bist_prepare()
469 		tx_burst_size = pattern_table[pattern].tx_burst_size;  in mv_ddr_odpg_bist_prepare()
477 	ddr3_tip_configure_odpg(0, access_type, 0, dir, pattern_table[pattern].num_of_phases_tx,  in mv_ddr_odpg_bist_prepare()
478 				tx_burst_size, pattern_table[pattern].num_of_phases_rx, burst_delay,  in mv_ddr_odpg_bist_prepare()
486 int mv_ddr_dm_vw_get(enum hws_pattern pattern, u32 cs, u8 *vw_vector)  in mv_ddr_dm_vw_get()  argument
508 	mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE,  in mv_ddr_dm_vw_get()
509 				 bist_offset, cs, pattern_table[pattern].num_of_phases_tx,  in mv_ddr_dm_vw_get()
510 				 (pattern == PATTERN_00) ? DM_DIR_DIRECT : DM_DIR_INVERSE);  in mv_ddr_dm_vw_get()
519 					pattern_table[pattern].num_of_phases_tx,  in mv_ddr_dm_vw_get()
520 					pattern_table[pattern].tx_burst_size,  in mv_ddr_dm_vw_get()
521 					pattern_table[pattern].num_of_phases_rx,  in mv_ddr_dm_vw_get()
541 				 bist_offset, cs, pattern_table[pattern].num_of_phases_tx,  in mv_ddr_dm_vw_get()
542 				 (pattern == PATTERN_00) ? DM_DIR_DIRECT : DM_DIR_INVERSE);  in mv_ddr_dm_vw_get()
552 					pattern_table[pattern].num_of_phases_tx,  in mv_ddr_dm_vw_get()
553 					pattern_table[pattern].tx_burst_size,  in mv_ddr_dm_vw_get()
554 					pattern_table[pattern].num_of_phases_rx,  in mv_ddr_dm_vw_get()
585 		mv_ddr_pattern_start_addr_set(pattern_table, pattern, odpg_addr);  in mv_ddr_dm_vw_get()
586 		mv_ddr_tip_bist(OPER_READ, 0, pattern, 0, &result);  in mv_ddr_dm_vw_get()