Lines Matching refs:dir
22 enum hws_dir dir, in ddr3_tip_bist_activate() argument
40 (dir == OPER_READ) ? (ODPG_WRBUF_RD_CTRL_ENA << ODPG_WRBUF_RD_CTRL_OFFS) : in ddr3_tip_bist_activate()
47 tx_burst_size = (dir == OPER_WRITE) ? in ddr3_tip_bist_activate()
49 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()
50 rd_mode = (dir == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()
51 ddr3_tip_configure_odpg(0, access_type, 0, dir, in ddr3_tip_bist_activate()
224 static int mv_ddr_tip_bist(enum hws_dir dir, u32 val, enum hws_pattern pattern, u32 cs, u32 *result) in mv_ddr_tip_bist() argument
233 RESULT_PER_BYTE, HWS_CONTROL_ELEMENT_ADLL, HWS_LOW2HIGH, dir, tm->if_act_mask, val, in mv_ddr_tip_bist()
442 enum hws_dir dir, enum hws_stress_jump stress_jump_addr, in mv_ddr_odpg_bist_prepare() argument
458 (dir == OPER_READ) ? (ODPG_WRBUF_RD_CTRL_ENA << ODPG_WRBUF_RD_CTRL_OFFS) : in mv_ddr_odpg_bist_prepare()
468 if (dir == OPER_WRITE) { in mv_ddr_odpg_bist_prepare()
477 ddr3_tip_configure_odpg(0, access_type, 0, dir, pattern_table[pattern].num_of_phases_tx, in mv_ddr_odpg_bist_prepare()