Lines Matching refs:dev_num
92 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num);
93 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
95 static int ddr3_tip_ddr3_auto_tune(u32 dev_num);
98 static int odt_test(u32 dev_num, enum hws_algo_type algo_type);
101 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
103 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
228 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
233 int ddr3_tip_tune_training_params(u32 dev_num, in ddr3_tip_tune_training_params() argument
279 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) in ddr3_tip_configure_cs() argument
289 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
296 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
303 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
309 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
318 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
324 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
335 int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_prm) in hws_ddr3_tip_init_controller() argument
348 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in hws_ddr3_tip_init_controller()
359 CHECK_STATUS(ddr3_tip_configure_phy(dev_num)); in hws_ddr3_tip_init_controller()
379 (dev_num, ACCESS_TYPE_MULTICAST, in hws_ddr3_tip_init_controller()
399 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
405 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
410 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
415 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
426 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
431 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
439 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
443 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
449 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
451 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) < MV_TIP_REV_3) { in hws_ddr3_tip_init_controller()
455 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
495 ddr3_tip_configure_cs(dev_num, if_id, cs_cnt, in hws_ddr3_tip_init_controller()
528 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
532 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
541 (dev_num, ACCESS_TYPE_MULTICAST, in hws_ddr3_tip_init_controller()
558 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
564 ddr3_tip_write_odt(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
566 ddr3_tip_set_timing(dev_num, access_type, if_id, freq); in hws_ddr3_tip_init_controller()
568 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) < MV_TIP_REV_3) { in hws_ddr3_tip_init_controller()
570 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
575 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
586 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
603 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
607 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
610 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
616 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
620 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
625 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
631 (dev_num, ACCESS_TYPE_MULTICAST, in hws_ddr3_tip_init_controller()
635 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) == MV_TIP_REV_3) { in hws_ddr3_tip_init_controller()
637 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
641 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
649 CHECK_STATUS(ddr3_tip_rank_control(dev_num, if_id)); in hws_ddr3_tip_init_controller()
656 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
659 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
667 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap); in hws_ddr3_tip_init_controller()
676 static int ddr3_tip_rev2_rank_control(u32 dev_num, u32 if_id) in ddr3_tip_rev2_rank_control() argument
679 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_rev2_rank_control()
724 (dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG, in ddr3_tip_rev2_rank_control()
730 static int ddr3_tip_rev3_rank_control(u32 dev_num, u32 if_id) in ddr3_tip_rev3_rank_control() argument
733 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_rev3_rank_control()
757 (dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG, in ddr3_tip_rev3_rank_control()
763 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id) in ddr3_tip_rank_control() argument
765 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) == MV_TIP_REV_2) in ddr3_tip_rank_control()
766 return ddr3_tip_rev2_rank_control(dev_num, if_id); in ddr3_tip_rank_control()
768 return ddr3_tip_rev3_rank_control(dev_num, if_id); in ddr3_tip_rank_control()
798 int ddr3_tip_validate_algo_components(u8 dev_num) in ddr3_tip_validate_algo_components() argument
818 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_dunit_mux_select_func, in ddr3_tip_validate_algo_components()
820 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_write, in ddr3_tip_validate_algo_components()
822 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_read, in ddr3_tip_validate_algo_components()
824 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_write, in ddr3_tip_validate_algo_components()
826 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_read, in ddr3_tip_validate_algo_components()
828 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_freq_config_info_func, in ddr3_tip_validate_algo_components()
830 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_set_freq_divider_func, in ddr3_tip_validate_algo_components()
832 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_clock_ratio, in ddr3_tip_validate_algo_components()
903 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type) in hws_ddr3_tip_run_alg() argument
915 return odt_test(dev_num, algo_type); in hws_ddr3_tip_run_alg()
919 status = ddr3_tip_ddr3_auto_tune(dev_num); in hws_ddr3_tip_run_alg()
942 static int odt_test(u32 dev_num, enum hws_algo_type algo_type) in odt_test() argument
964 ret = ddr3_tip_ddr3_auto_tune(dev_num); in odt_test()
982 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable) in hws_ddr3_tip_select_ddr_controller() argument
984 return config_func_info[dev_num]. in hws_ddr3_tip_select_ddr_controller()
985 tip_dunit_mux_select_func((u8)dev_num, enable); in hws_ddr3_tip_select_ddr_controller()
991 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access, in ddr3_tip_if_write() argument
994 config_func_info[dev_num].mv_ddr_dunit_write(reg_addr, mask, data_value); in ddr3_tip_if_write()
1002 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access, in ddr3_tip_if_read() argument
1005 config_func_info[dev_num].mv_ddr_dunit_read(reg_addr, mask, data); in ddr3_tip_if_read()
1013 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_if_polling() argument
1038 ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_if_polling()
1065 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read() argument
1069 return config_func_info[dev_num]. in ddr3_tip_bus_read()
1076 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access, in ddr3_tip_bus_write() argument
1081 return config_func_info[dev_num]. in ddr3_tip_bus_write()
1089 int ddr3_tip_bus_read_modify_write(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_bus_read_modify_write() argument
1108 (dev_num, if_id, ACCESS_TYPE_UNICAST, phy_id, in ddr3_tip_bus_read_modify_write()
1112 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bus_read_modify_write()
1123 int adll_calibration(u32 dev_num, enum hws_access_type access_type, in adll_calibration() argument
1128 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in adll_calibration()
1133 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1137 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1140 CHECK_STATUS(config_func_info[dev_num]. in adll_calibration()
1141 tip_get_freq_config_info_func((u8)dev_num, frequency, in adll_calibration()
1147 (dev_num, access_type, if_id, bus_cnt, in adll_calibration()
1151 (dev_num, access_type, if_id, bus_cnt, in adll_calibration()
1158 (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_cnt, in adll_calibration()
1162 (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_cnt, in adll_calibration()
1169 (dev_num, access_type, if_id, DRAM_PHY_CFG_REG, in adll_calibration()
1173 (dev_num, access_type, if_id, DRAM_PHY_CFG_REG, in adll_calibration()
1177 if (ddr3_tip_if_polling(dev_num, access_type, if_id, in adll_calibration()
1186 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1190 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1196 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_freq_set() argument
1212 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_freq_set()
1219 ("dev %d access %d IF %d freq %d\n", dev_num, in ddr3_tip_freq_set()
1239 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs, in ddr3_tip_freq_set()
1279 dev_num, access_type, if_id, in ddr3_tip_freq_set()
1299 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, in ddr3_tip_freq_set()
1307 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1311 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1316 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1320 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1326 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1329 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1332 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1335 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1341 (dev_num, access_type, if_id, DFS_REG, 0x4, in ddr3_tip_freq_set()
1344 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_freq_set()
1363 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_INTERLEAVE_WA) == 1) { in ddr3_tip_freq_set()
1365 if (config_func_info[dev_num].tip_get_clock_ratio(frequency) == 1) { in ddr3_tip_freq_set()
1368 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1374 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1378 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_freq_set()
1382 config_func_info[dev_num].tip_set_freq_divider_func(dev_num, if_id, in ddr3_tip_freq_set()
1387 (dev_num, access_type, if_id, DFS_REG, in ddr3_tip_freq_set()
1390 (dev_num, access_type, if_id, DFS_REG, in ddr3_tip_freq_set()
1399 (dev_num, access_type, if_id, DFS_REG, in ddr3_tip_freq_set()
1405 (dev_num, access_type, if_id, 0x1874, in ddr3_tip_freq_set()
1408 (dev_num, access_type, if_id, 0x1884, in ddr3_tip_freq_set()
1411 (dev_num, access_type, if_id, 0x1894, in ddr3_tip_freq_set()
1414 (dev_num, access_type, if_id, 0x18a4, in ddr3_tip_freq_set()
1420 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1424 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1428 CHECK_STATUS(config_func_info[dev_num]. in ddr3_tip_freq_set()
1429 tip_get_freq_config_info_func(dev_num, frequency, in ddr3_tip_freq_set()
1437 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_freq_set()
1445 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_freq_set()
1452 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1457 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1463 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x3ff03ff, in ddr3_tip_freq_set()
1472 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1476 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1480 ddr3_tip_set_timing(dev_num, access_type, if_id, frequency); in ddr3_tip_freq_set()
1483 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap); in ddr3_tip_freq_set()
1488 (dev_num, access_type, if_id, DFS_REG, 0, in ddr3_tip_freq_set()
1491 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x8, DFS_REG, in ddr3_tip_freq_set()
1499 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1502 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f, in ddr3_tip_freq_set()
1510 (dev_num, access_type, if_id, DFS_REG, 0, in ddr3_tip_freq_set()
1514 (dev_num, access_type, if_id, DUNIT_MMASK_REG, in ddr3_tip_freq_set()
1522 (dev_num, access_type, if_id, MR0_REG, in ddr3_tip_freq_set()
1533 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, in ddr3_tip_freq_set()
1541 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, in ddr3_tip_freq_set()
1545 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, in ddr3_tip_freq_set()
1553 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG, 0xf, 0xf)); in ddr3_tip_freq_set()
1556 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG, in ddr3_tip_freq_set()
1564 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0, in ddr3_tip_freq_set()
1569 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD2, in ddr3_tip_freq_set()
1573 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, in ddr3_tip_freq_set()
1586 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_write_odt() argument
1597 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_odt()
1600 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_odt()
1603 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, in ddr3_tip_write_odt()
1610 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_odt()
1619 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_set_timing() argument
1638 t_hclk = MEGA / (freq / config_func_info[dev_num].tip_get_clock_ratio(frequency)); in ddr3_tip_set_timing()
1712 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1739 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1742 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1746 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1750 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DDR_TIMING_REG, in ddr3_tip_set_timing()
1764 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset) in ddr3_tip_write_cs_result() argument
1767 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_write_cs_result()
1780 ddr3_tip_bus_read(dev_num, if_id, in ddr3_tip_write_cs_result()
1786 ddr3_tip_bus_write(dev_num, in ddr3_tip_write_cs_result()
1804 int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask) in ddr3_tip_write_mrs_cmd() argument
1809 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_write_mrs_cmd()
1814 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_write_mrs_cmd()
1821 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0, in ddr3_tip_write_mrs_cmd()
1835 int ddr3_tip_reset_fifo_ptr(u32 dev_num) in ddr3_tip_reset_fifo_ptr() argument
1840 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1846 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1850 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1854 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1857 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1861 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1865 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1874 int ddr3_tip_ddr3_reset_phy_regs(u32 dev_num) in ddr3_tip_ddr3_reset_phy_regs() argument
1877 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_ddr3_reset_phy_regs()
1886 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_ddr3_reset_phy_regs()
1892 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1897 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1901 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1905 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1909 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1913 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1917 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1921 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1925 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1935 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_ddr3_reset_phy_regs()
1946 int ddr3_tip_restore_dunit_regs(u32 dev_num) in ddr3_tip_restore_dunit_regs() argument
1952 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_restore_dunit_regs()
1955 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_restore_dunit_regs()
1959 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_restore_dunit_regs()
1967 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_restore_dunit_regs()
1976 int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2) in ddr3_tip_adll_regs_bypass() argument
1979 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_adll_regs_bypass()
1987 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_adll_regs_bypass()
1991 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_adll_regs_bypass()
2003 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) in ddr3_tip_ddr3_training_main_flow() argument
2019 CHECK_STATUS(print_device_info((u8)dev_num)); in ddr3_tip_ddr3_training_main_flow()
2023 ddr3_tip_validate_algo_components(dev_num); in ddr3_tip_ddr3_training_main_flow()
2026 CHECK_STATUS(ddr3_tip_ddr3_reset_phy_regs(dev_num)); in ddr3_tip_ddr3_training_main_flow()
2036 config_func_info[dev_num].tip_set_freq_divider_func( in ddr3_tip_ddr3_training_main_flow()
2037 (u8)dev_num, if_id, freq); in ddr3_tip_ddr3_training_main_flow()
2046 adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq); in ddr3_tip_ddr3_training_main_flow()
2052 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2063 ret = hws_ddr3_tip_init_controller(dev_num, &init_cntr_prm); in ddr3_tip_ddr3_training_main_flow()
2065 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2075 ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq); in ddr3_tip_ddr3_training_main_flow()
2087 ddr3_tip_adll_regs_bypass(dev_num, 0, 0x1f); in ddr3_tip_ddr3_training_main_flow()
2095 ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_ddr3_training_main_flow()
2098 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2111 ret = ddr3_tip_dynamic_write_leveling(dev_num, 1); in ddr3_tip_ddr3_training_main_flow()
2113 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2128 ret = ddr3_tip_load_all_pattern_to_mem(dev_num); in ddr3_tip_ddr3_training_main_flow()
2130 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2143 ddr3_tip_adll_regs_bypass(dev_num, phy_reg1_val, 0); in ddr3_tip_ddr3_training_main_flow()
2157 ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_ddr3_training_main_flow()
2160 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2174 ret = ddr3_tip_dynamic_write_leveling(dev_num, 0); in ddr3_tip_ddr3_training_main_flow()
2177 ret = ddr3_tip_legacy_dynamic_write_leveling(dev_num); in ddr3_tip_ddr3_training_main_flow()
2181 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2196 ret = ddr3_tip_load_all_pattern_to_mem(dev_num); in ddr3_tip_ddr3_training_main_flow()
2198 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2216 ret = ddr3_tip_dynamic_read_leveling(dev_num, medium_freq); in ddr3_tip_ddr3_training_main_flow()
2219 ret = ddr3_tip_legacy_dynamic_read_leveling(dev_num); in ddr3_tip_ddr3_training_main_flow()
2223 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2236 ret = ddr3_tip_dynamic_write_leveling_supp(dev_num); in ddr3_tip_ddr3_training_main_flow()
2238 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2253 ret = ddr3_tip_pbs_rx(dev_num); in ddr3_tip_ddr3_training_main_flow()
2255 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2272 ret = ddr3_tip_pbs_tx(dev_num); in ddr3_tip_ddr3_training_main_flow()
2274 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2294 ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_ddr3_training_main_flow()
2299 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2312 ret = ddr3_tip_dynamic_write_leveling(dev_num, 0); in ddr3_tip_ddr3_training_main_flow()
2314 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2326 ret = ddr3_tip_load_all_pattern_to_mem(dev_num); in ddr3_tip_ddr3_training_main_flow()
2328 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2341 ret = ddr3_tip_dynamic_read_leveling(dev_num, tm-> in ddr3_tip_ddr3_training_main_flow()
2345 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2360 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2377 ret = ddr3_tip_vref(dev_num); in ddr3_tip_ddr3_training_main_flow()
2381 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2400 ret = ddr3_tip_centralization_rx(dev_num); in ddr3_tip_ddr3_training_main_flow()
2402 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2421 ret = ddr3_tip_dynamic_write_leveling_supp(dev_num); in ddr3_tip_ddr3_training_main_flow()
2423 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2443 ret = ddr3_tip_centralization_tx(dev_num); in ddr3_tip_ddr3_training_main_flow()
2445 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2460 CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num)); in ddr3_tip_ddr3_training_main_flow()
2463 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2471 static int ddr3_tip_ddr3_auto_tune(u32 dev_num) in ddr3_tip_ddr3_auto_tune() argument
2484 status = ddr3_tip_ddr3_training_main_flow(dev_num); in ddr3_tip_ddr3_auto_tune()
2488 run_xsb_test(dev_num, xsb_validation_base_address, 1, 1, in ddr3_tip_ddr3_auto_tune()
2493 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_auto_tune()
2496 CHECK_STATUS(ddr3_tip_print_log(dev_num, window_mem_addr)); in ddr3_tip_ddr3_auto_tune()
2500 CHECK_STATUS(ddr3_tip_print_stability_log(dev_num)); in ddr3_tip_ddr3_auto_tune()
2540 int ddr3_tip_enable_init_sequence(u32 dev_num) in ddr3_tip_enable_init_sequence() argument
2544 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_enable_init_sequence()
2548 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, 0, in ddr3_tip_enable_init_sequence()
2555 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1, in ddr3_tip_enable_init_sequence()
2577 (dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_enable_init_sequence()
2586 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table) in ddr3_tip_register_dq_table() argument