94 			      u32 if_id, u32 cl_value, u32 cwl_value);
1199 	u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0,  in ddr3_tip_freq_set()  local
1258 			cwl_value =  in ddr3_tip_freq_set()
1267 			cwl_value = mv_ddr_cwl_calc(tclk);  in ddr3_tip_freq_set()
1268 			if (cwl_value == 0) {  in ddr3_tip_freq_set()
1274 			cwl_value = mv_ddr_cwl_val_get(speed_bin_index, frequency);  in ddr3_tip_freq_set()
1391 			      (cwl_mask_table[cwl_value] << 12), 0x7000));  in ddr3_tip_freq_set()
1525 		val = (cwl_mask_table[cwl_value] << 3) | g_rtt_wr;  in ddr3_tip_freq_set()
1538 		val = ((cl_value - cwl_value + 1) << 4) |  in ddr3_tip_freq_set()
1539 			((cl_value - cwl_value + 6) << 8) |  in ddr3_tip_freq_set()
1544 		val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);  in ddr3_tip_freq_set()
1568 		val = (cwl_mask_table[cwl_value] << 3) | g_rtt_wr;  in ddr3_tip_freq_set()
1587 			      u32 if_id, u32 cl_value, u32 cwl_value)  in ddr3_tip_write_odt()  argument
1590 	u32 val = (cl_value - cwl_value + 6);  in ddr3_tip_write_odt()
1592 	val = ((cl_value - cwl_value + 1) << 4) | ((val & 0xf) << 8) |  in ddr3_tip_write_odt()
1599 	val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);  in ddr3_tip_write_odt()