Lines Matching refs:cs_num
12 #define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num]) argument
279 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) in ddr3_tip_configure_cs() argument
290 SDRAM_ADDR_CTRL_REG, (data << (cs_num * 4)), in ddr3_tip_configure_cs()
291 0x3 << (cs_num * 4))); in ddr3_tip_configure_cs()
298 (addr_hi << (2 + cs_num * 4)), in ddr3_tip_configure_cs()
299 0x3 << (2 + cs_num * 4))); in ddr3_tip_configure_cs()
305 data_high << (20 + cs_num), 1 << (20 + cs_num))); in ddr3_tip_configure_cs()
310 SDRAM_ADDR_CTRL_REG, 1 << (16 + cs_num), in ddr3_tip_configure_cs()
311 1 << (16 + cs_num))); in ddr3_tip_configure_cs()
313 switch (cs_num) { in ddr3_tip_configure_cs()
319 DUNIT_CTRL_LOW_REG, (enable << (cs_num + 11)), in ddr3_tip_configure_cs()
320 1 << (cs_num + 11))); in ddr3_tip_configure_cs()
338 u32 cs_num; in hws_ddr3_tip_init_controller() local
598 cs_num = mv_ddr_cs_num_get(); in hws_ddr3_tip_init_controller()
599 t2t = (cs_num == 1) ? 0 : 1; in hws_ddr3_tip_init_controller()
1209 u32 cs_num; in ddr3_tip_freq_set() local
1358 cs_num = mv_ddr_cs_num_get(); in ddr3_tip_freq_set()
1359 t2t = (cs_num == 1) ? 0 : 1; in ddr3_tip_freq_set()
1766 u32 if_id, bus_num, cs_bitmask, data_val, cs_num; in ddr3_tip_write_cs_result() local
1779 cs_num = GET_CS_FROM_MASK(cs_bitmask); in ddr3_tip_write_cs_result()
1792 (cs_num * 0x4), in ddr3_tip_write_cs_result()
2871 unsigned int cs_num = mv_ddr_cs_num_get(); in mv_ddr_misl_phy_odt_p_get() local
2874 if (cs_num > 0 && cs_num <= MAX_CS_NUM) in mv_ddr_misl_phy_odt_p_get()
2875 odt_p = mv_ddr_misl_phy_odt_calc(tm->edata.phy_edata.odt_p[cs_num - 1]); in mv_ddr_misl_phy_odt_p_get()
2886 unsigned int cs_num = mv_ddr_cs_num_get(); in mv_ddr_misl_phy_odt_n_get() local
2889 if (cs_num > 0 && cs_num <= MAX_CS_NUM) in mv_ddr_misl_phy_odt_n_get()
2890 odt_n = mv_ddr_misl_phy_odt_calc(tm->edata.phy_edata.odt_n[cs_num - 1]); in mv_ddr_misl_phy_odt_n_get()