193 		    as_bus_params[sphy].is_dqs_swap == 1) {  in ddr3_tip_pad_inv()
204 		if (tm->interface_params[0].as_bus_params[sphy].  in ddr3_tip_pad_inv()
374 					as_bus_params[bus_index].mirror_enable_bitmask;  in hws_ddr3_tip_init_controller()
483 					as_bus_params[bus_cnt].cs_bitmask;  in hws_ddr3_tip_init_controller()
684 		data_value |= tm->interface_params[if_id].as_bus_params[bus_cnt].  in ddr3_tip_rev2_rank_control()
687 		if (tm->interface_params[if_id].as_bus_params[bus_cnt].  in ddr3_tip_rev2_rank_control()
693 			if ((tm->interface_params[if_id].as_bus_params[bus_cnt].  in ddr3_tip_rev2_rank_control()
696 					      as_bus_params[bus_cnt].  in ddr3_tip_rev2_rank_control()
700 			if ((tm->interface_params[if_id].as_bus_params[bus_cnt].  in ddr3_tip_rev2_rank_control()
703 					      as_bus_params[bus_cnt].  in ddr3_tip_rev2_rank_control()
707 			if ((tm->interface_params[if_id].as_bus_params[bus_cnt].  in ddr3_tip_rev2_rank_control()
710 					      as_bus_params[bus_cnt].  in ddr3_tip_rev2_rank_control()
714 			if ((tm->interface_params[if_id].as_bus_params[bus_cnt].  in ddr3_tip_rev2_rank_control()
717 					      as_bus_params[bus_cnt].  in ddr3_tip_rev2_rank_control()
739 		     as_bus_params[0].cs_bitmask !=  in ddr3_tip_rev3_rank_control()
741 		     as_bus_params[bus_cnt].cs_bitmask) ||  in ddr3_tip_rev3_rank_control()
743 		     as_bus_params[0].mirror_enable_bitmask !=  in ddr3_tip_rev3_rank_control()
745 		     as_bus_params[bus_cnt].mirror_enable_bitmask))  in ddr3_tip_rev3_rank_control()
752 		as_bus_params[0].cs_bitmask;  in ddr3_tip_rev3_rank_control()
754 		as_bus_params[0].mirror_enable_bitmask << 4;  in ddr3_tip_rev3_rank_control()
1294 				as_bus_params[bus_index].mirror_enable_bitmask;  in ddr3_tip_freq_set()
1777 				as_bus_params[bus_num].cs_bitmask;  in ddr3_tip_write_cs_result()
2571 				as_bus_params[bus_index].mirror_enable_bitmask;  in ddr3_tip_enable_init_sequence()