Lines Matching refs:MAX_INTERFACE_NUM
39 enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
347 u32 data_read[MAX_INTERFACE_NUM]; in hws_ddr3_tip_init_controller()
363 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
647 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
1018 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_if_polling()
1025 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_if_polling()
1099 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_bus_read_modify_write()
1211 u32 cs_mask[MAX_INTERFACE_NUM]; in ddr3_tip_freq_set()
1226 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_freq_set()
1234 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_freq_set()
1770 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_cs_result()
1811 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
1819 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
1880 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_reset_phy_regs()
1982 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_adll_regs_bypass()
2034 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_ddr3_training_main_flow()
2479 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_auto_tune()
2504 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_auto_tune()
2551 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_enable_init_sequence()