Lines Matching +full:de +full:- +full:assertion
1 // SPDX-License-Identifier: GPL-2.0
25 /* in case of ddr4 do not run ddr3_tip_write_additional_odt_setting function - mc odt always 'on'
66 u32 g_zpri_data = PARAM_UNDEFINED; /* controller data - P drive strength */
67 u32 g_znri_data = PARAM_UNDEFINED; /* controller data - N drive strength */
68 u32 g_zpri_ctrl = PARAM_UNDEFINED; /* controller C/A - P drive strength */
69 u32 g_znri_ctrl = PARAM_UNDEFINED; /* controller C/A - N drive strength */
71 u32 g_zpodt_data = PARAM_UNDEFINED; /* controller data - P ODT */
72 u32 g_znodt_data = PARAM_UNDEFINED; /* controller data - N ODT */
73 u32 g_zpodt_ctrl = PARAM_UNDEFINED; /* controller data - P ODT */
74 u32 g_znodt_ctrl = PARAM_UNDEFINED; /* controller data - N ODT */
112 0x0, /* TODO: placeholder for 16-Mbit die capacity */
113 0x0, /* TODO: placeholder for 32-Mbit die capacity */
114 0x0, /* TODO: placeholder for 12-Mbit die capacity */
115 0x0 /* TODO: placeholder for 24-Mbit die capacity */
191 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy); in ddr3_tip_pad_inv()
192 if (tm->interface_params[0]. in ddr3_tip_pad_inv()
204 if (tm->interface_params[0].as_bus_params[sphy]. in ddr3_tip_pad_inv()
236 if (params->ck_delay != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
237 ck_delay = params->ck_delay; in ddr3_tip_tune_training_params()
238 if (params->phy_reg3_val != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
239 phy_reg3_val = params->phy_reg3_val; in ddr3_tip_tune_training_params()
240 if (params->g_rtt_nom != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
241 g_rtt_nom = params->g_rtt_nom; in ddr3_tip_tune_training_params()
242 if (params->g_rtt_wr != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
243 g_rtt_wr = params->g_rtt_wr; in ddr3_tip_tune_training_params()
244 if (params->g_dic != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
245 g_dic = params->g_dic; in ddr3_tip_tune_training_params()
246 if (params->g_odt_config != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
247 g_odt_config = params->g_odt_config; in ddr3_tip_tune_training_params()
248 if (params->g_zpri_data != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
249 g_zpri_data = params->g_zpri_data; in ddr3_tip_tune_training_params()
250 if (params->g_znri_data != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
251 g_znri_data = params->g_znri_data; in ddr3_tip_tune_training_params()
252 if (params->g_zpri_ctrl != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
253 g_zpri_ctrl = params->g_zpri_ctrl; in ddr3_tip_tune_training_params()
254 if (params->g_znri_ctrl != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
255 g_znri_ctrl = params->g_znri_ctrl; in ddr3_tip_tune_training_params()
256 if (params->g_zpodt_data != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
257 g_zpodt_data = params->g_zpodt_data; in ddr3_tip_tune_training_params()
258 if (params->g_znodt_data != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
259 g_znodt_data = params->g_znodt_data; in ddr3_tip_tune_training_params()
260 if (params->g_zpodt_ctrl != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
261 g_zpodt_ctrl = params->g_zpodt_ctrl; in ddr3_tip_tune_training_params()
262 if (params->g_znodt_ctrl != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
263 g_znodt_ctrl = params->g_znodt_ctrl; in ddr3_tip_tune_training_params()
264 if (params->g_rtt_park != PARAM_UNDEFINED) in ddr3_tip_tune_training_params()
265 g_rtt_park = params->g_rtt_park; in ddr3_tip_tune_training_params()
286 data = (tm->interface_params[if_id].bus_width == in ddr3_tip_configure_cs()
292 mem_index = tm->interface_params[if_id].memory_size; in ddr3_tip_configure_cs()
351 enum mv_ddr_freq freq = tm->interface_params[0].memory_freq; in hws_ddr3_tip_init_controller()
355 init_cntr_prm->do_mrs_phy, in hws_ddr3_tip_init_controller()
356 init_cntr_prm->is_ctrl64_bit)); in hws_ddr3_tip_init_controller()
358 if (init_cntr_prm->init_phy == 1) { in hws_ddr3_tip_init_controller()
363 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
364 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in hws_ddr3_tip_init_controller()
371 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_index); in hws_ddr3_tip_init_controller()
373 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
385 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
391 if (MV_DDR_IS_HALF_BUS_DRAM_MODE(tm->bus_act_mask, octets_per_if_num)) in hws_ddr3_tip_init_controller()
403 /* Interleave first command pre-charge enable (TBD) */ in hws_ddr3_tip_init_controller()
409 /* Reset divider_b assert -> de-assert */ in hws_ddr3_tip_init_controller()
428 if (init_cntr_prm->is_ctrl64_bit) { in hws_ddr3_tip_init_controller()
447 /* Pad calibration control - enable */ in hws_ddr3_tip_init_controller()
453 /* CS1 mirroring enable + w/a for JIRA DUNIT-14581 */ in hws_ddr3_tip_init_controller()
473 (tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
480 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in hws_ddr3_tip_init_controller()
482 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
500 if (init_cntr_prm->do_mrs_phy) { in hws_ddr3_tip_init_controller()
511 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
514 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
545 /* MR2 - Part of the Generic code */ in hws_ddr3_tip_init_controller()
553 ((tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
577 (init_cntr_prm->is_ctrl64_bit ? in hws_ddr3_tip_init_controller()
588 (init_cntr_prm->msys_init << 7), (1 << 7))); in hws_ddr3_tip_init_controller()
590 timing = tm->interface_params[if_id].timing; in hws_ddr3_tip_init_controller()
613 /* move the block to ddr3_tip_set_timing - end */ in hws_ddr3_tip_init_controller()
639 /* wa: controls control sub-phy outputs floating during self-refresh */ in hws_ddr3_tip_init_controller()
647 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
648 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in hws_ddr3_tip_init_controller()
651 if (init_cntr_prm->do_mrs_phy) in hws_ddr3_tip_init_controller()
654 /* Pad calibration control - disable */ in hws_ddr3_tip_init_controller()
683 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_rev2_rank_control()
684 data_value |= tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
687 if (tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
693 if ((tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
695 data_value |= tm->interface_params[if_id]. in ddr3_tip_rev2_rank_control()
700 if ((tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
702 data_value |= tm->interface_params[if_id]. in ddr3_tip_rev2_rank_control()
707 if ((tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
709 data_value |= tm->interface_params[if_id]. in ddr3_tip_rev2_rank_control()
714 if ((tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
716 data_value |= tm->interface_params[if_id]. in ddr3_tip_rev2_rank_control()
737 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_rev3_rank_control()
738 if ((tm->interface_params[if_id]. in ddr3_tip_rev3_rank_control()
740 tm->interface_params[if_id]. in ddr3_tip_rev3_rank_control()
742 (tm->interface_params[if_id]. in ddr3_tip_rev3_rank_control()
744 tm->interface_params[if_id]. in ddr3_tip_rev3_rank_control()
751 data_value |= tm->interface_params[if_id]. in ddr3_tip_rev3_rank_control()
753 data_value |= tm->interface_params[if_id]. in ddr3_tip_rev3_rank_control()
847 if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) { in ddr3_pre_algo_config()
855 if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) || in ddr3_pre_algo_config()
856 (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) || in ddr3_pre_algo_config()
857 (DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))) { in ddr3_pre_algo_config()
882 printf("DDR3 Post Run Alg - FAILED 0x%x\n", status); in ddr3_post_algo_config()
887 if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) || in ddr3_post_algo_config()
888 (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) || in ddr3_post_algo_config()
889 (DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))) { in ddr3_post_algo_config()
909 printf("DDR3 Pre Algo Config - FAILED 0x%x\n", status); in hws_ddr3_tip_run_alg()
931 printf("DDR3 Post Algo Config - FAILED 0x%x\n", status); in hws_ddr3_tip_run_alg()
1025 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_if_polling()
1033 VALIDATE_IF_ACTIVE(tm->if_act_mask, interface_num); in ddr3_tip_if_polling()
1087 * Phy read-modify-write
1099 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_bus_read_modify_write()
1106 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_bus_read_modify_write()
1131 /* Reset Diver_b assert -> de-assert */ in adll_calibration()
1145 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in adll_calibration()
1167 /* DUnit to Phy drive post edge, ADLL reset assert de-assert */ in adll_calibration()
1184 /* pup data_pup reset assert-> deassert */ in adll_calibration()
1215 enum mv_ddr_timing timing = tm->interface_params[if_id].timing; in ddr3_tip_freq_set()
1226 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_freq_set()
1232 /* calculate interface cs mask - Oferb 4/11 */ in ddr3_tip_freq_set()
1234 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_freq_set()
1236 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_freq_set()
1245 * moti b - need to remove the loop for multicas access functions in ddr3_tip_freq_set()
1249 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_freq_set()
1253 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_freq_set()
1254 if (tm->interface_params[if_id].memory_freq == in ddr3_tip_freq_set()
1257 tm->interface_params[if_id].cas_l; in ddr3_tip_freq_set()
1259 tm->interface_params[if_id].cas_wl; in ddr3_tip_freq_set()
1260 } else if (tm->cfg_src == MV_DDR_CFG_SPD) { in ddr3_tip_freq_set()
1262 cl_value = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk); in ddr3_tip_freq_set()
1291 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_freq_set()
1293 tm->interface_params[if_id]. in ddr3_tip_freq_set()
1318 /* DFS - block transactions */ in ddr3_tip_freq_set()
1339 /* DFS - Enter Self-Refresh */ in ddr3_tip_freq_set()
1385 /* DFS - CL/CWL/WR parameters after exiting SR */ in ddr3_tip_freq_set()
1418 /* Reset divider_b assert -> de-assert */ in ddr3_tip_freq_set()
1435 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_freq_set()
1450 /* Dunit to PHY drive post edge, ADLL reset assert -> de-assert */ in ddr3_tip_freq_set()
1470 /* pup data_pup reset assert-> deassert */ in ddr3_tip_freq_set()
1479 /* Set proper timing params before existing Self-Refresh */ in ddr3_tip_freq_set()
1512 /* Controller to MBUS Retry - normal */ in ddr3_tip_freq_set()
1524 /* MR2: CWL = 10 , Auto Self-Refresh - disable */ in ddr3_tip_freq_set()
1527 * nklein 24.10.13 - should not be here - leave value as set in in ddr3_tip_freq_set()
1529 * val |= ((tm->interface_params[if_id]. in ddr3_tip_freq_set()
1532 /* nklein 24.10.13 - see above comment */ in ddr3_tip_freq_set()
1538 val = ((cl_value - cwl_value + 1) << 4) | in ddr3_tip_freq_set()
1539 ((cl_value - cwl_value + 6) << 8) | in ddr3_tip_freq_set()
1540 ((cl_value - 1) << 12) | ((cl_value + 6) << 16); in ddr3_tip_freq_set()
1544 val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12); in ddr3_tip_freq_set()
1560 /* re-write CL */ in ddr3_tip_freq_set()
1567 /* re-write CWL */ in ddr3_tip_freq_set()
1590 u32 val = (cl_value - cwl_value + 6); in ddr3_tip_write_odt()
1592 val = ((cl_value - cwl_value + 1) << 4) | ((val & 0xf) << 8) | in ddr3_tip_write_odt()
1593 (((cl_value - 1) & 0xf) << 12) | in ddr3_tip_write_odt()
1595 val |= (((cl_value - 1) >> 4) << 22) | (((cl_value + 6) >> 4) << 23); in ddr3_tip_write_odt()
1599 val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12); in ddr3_tip_write_odt()
1633 speed_bin_index = tm->interface_params[if_id].speed_bin_index; in ddr3_tip_set_timing()
1634 memory_size = tm->interface_params[if_id].memory_size; in ddr3_tip_set_timing()
1635 page_size = mv_ddr_page_size_get(tm->interface_params[if_id].bus_width, memory_size); in ddr3_tip_set_timing()
1640 t_refi = (tm->interface_params[if_id].interface_temp == MV_DDR_TEMP_HIGH) ? TREFI_HIGH : TREFI_LOW; in ddr3_tip_set_timing()
1688 val = (((t_ras - 1) & SDRAM_TIMING_LOW_TRAS_MASK) << SDRAM_TIMING_LOW_TRAS_OFFS) | in ddr3_tip_set_timing()
1689 (((t_rcd - 1) & SDRAM_TIMING_LOW_TRCD_MASK) << SDRAM_TIMING_LOW_TRCD_OFFS) | in ddr3_tip_set_timing()
1690 (((t_rcd - 1) >> SDRAM_TIMING_LOW_TRCD_OFFS & SDRAM_TIMING_HIGH_TRCD_MASK) in ddr3_tip_set_timing()
1692 (((t_rp - 1) & SDRAM_TIMING_LOW_TRP_MASK) << SDRAM_TIMING_LOW_TRP_OFFS) | in ddr3_tip_set_timing()
1693 (((t_rp - 1) >> SDRAM_TIMING_LOW_TRP_MASK & SDRAM_TIMING_HIGH_TRP_MASK) in ddr3_tip_set_timing()
1695 (((t_wr - 1) & SDRAM_TIMING_LOW_TWR_MASK) << SDRAM_TIMING_LOW_TWR_OFFS) | in ddr3_tip_set_timing()
1696 (((t_wtr - 1) & SDRAM_TIMING_LOW_TWTR_MASK) << SDRAM_TIMING_LOW_TWTR_OFFS) | in ddr3_tip_set_timing()
1697 ((((t_ras - 1) >> 4) & SDRAM_TIMING_LOW_TRAS_HIGH_MASK) << SDRAM_TIMING_LOW_TRAS_HIGH_OFFS) | in ddr3_tip_set_timing()
1698 (((t_rrd - 1) & SDRAM_TIMING_LOW_TRRD_MASK) << SDRAM_TIMING_LOW_TRRD_OFFS) | in ddr3_tip_set_timing()
1699 (((t_rtp - 1) & SDRAM_TIMING_LOW_TRTP_MASK) << SDRAM_TIMING_LOW_TRTP_OFFS); in ddr3_tip_set_timing()
1719 val = (((t_rfc - 1) & SDRAM_TIMING_HIGH_TRFC_MASK) << SDRAM_TIMING_HIGH_TRFC_OFFS) | in ddr3_tip_set_timing()
1723 … ((((t_rfc - 1) >> 7) & SDRAM_TIMING_HIGH_TRFC_HIGH_MASK) << SDRAM_TIMING_HIGH_TRFC_HIGH_OFFS) | in ddr3_tip_set_timing()
1726 (((t_mod - 1) & SDRAM_TIMING_HIGH_TMOD_MASK) << SDRAM_TIMING_HIGH_TMOD_OFFS) | in ddr3_tip_set_timing()
1727 … ((((t_mod - 1) >> 4) & SDRAM_TIMING_HIGH_TMOD_HIGH_MASK) << SDRAM_TIMING_HIGH_TMOD_HIGH_OFFS); in ddr3_tip_set_timing()
1747 SDRAM_ADDR_CTRL_REG, (t_faw - 1) << T_FAW_OFFS, in ddr3_tip_set_timing()
1751 (t_pd - 1) << DDR_TIMING_TPD_OFFS | in ddr3_tip_set_timing()
1752 (t_xpdll - 1) << DDR_TIMING_TXPDLL_OFFS, in ddr3_tip_set_timing()
1770 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_cs_result()
1771 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_write_cs_result()
1774 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_write_cs_result()
1776 tm->interface_params[if_id]. in ddr3_tip_write_cs_result()
1811 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
1812 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_write_mrs_cmd()
1819 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
1820 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_write_mrs_cmd()
1853 /* Reset read fifo assertion */ in ddr3_tip_reset_fifo_ptr()
1880 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_reset_phy_regs()
1881 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_ddr3_reset_phy_regs()
1884 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, phy_id); in ddr3_tip_ddr3_reset_phy_regs()
1933 /* PHY register 0xdb bits[5:0] - configure to 63 */ in ddr3_tip_ddr3_reset_phy_regs()
1982 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_adll_regs_bypass()
1983 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_adll_regs_bypass()
1985 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, phy_id); in ddr3_tip_adll_regs_bypass()
2014 enum mv_ddr_freq freq = tm->interface_params[0].memory_freq; in ddr3_tip_ddr3_training_main_flow()
2035 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_ddr3_training_main_flow()
2291 freq_tbl[tm-> in ddr3_tip_ddr3_training_main_flow()
2296 tm->interface_params[first_active_if]. in ddr3_tip_ddr3_training_main_flow()
2341 ret = ddr3_tip_dynamic_read_leveling(dev_num, tm-> in ddr3_tip_ddr3_training_main_flow()
2358 ret = mv_ddr_rl_dqs_burst(0, 0, tm->interface_params[0].memory_freq); in ddr3_tip_ddr3_training_main_flow()
2479 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_auto_tune()
2504 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_auto_tune()
2551 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_enable_init_sequence()
2552 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_enable_init_sequence()
2568 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_enable_init_sequence()
2570 tm->interface_params[if_id]. in ddr3_tip_enable_init_sequence()
2602 bit_end = BUS_WIDTH_IN_BITS - 1; in ddr3_tip_is_pup_lock()
2657 return (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == in hws_ddr3_get_bus_width()
2665 return (tm->interface_params[if_id].bus_width == in hws_ddr3_get_device_width()
2673 if (tm->interface_params[if_id].memory_size >= in hws_ddr3_get_device_size()
2677 tm->interface_params[if_id].memory_size)); in hws_ddr3_get_device_size()
2680 return 1 << tm->interface_params[if_id].memory_size; in hws_ddr3_get_device_size()
2734 physical_mem_size = mem_size[tm->interface_params[0].memory_size]; in hws_ddr3_cs_base_adr_calc()
2738 * 16bit mem device can be twice more - no need in less in hws_ddr3_cs_base_adr_calc()
2827 unsigned int drv_data_p = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_data_p); in mv_ddr_misl_phy_drv_data_p_get()
2838 unsigned int drv_data_n = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_data_n); in mv_ddr_misl_phy_drv_data_n_get()
2849 unsigned int drv_ctrl_p = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_ctrl_p); in mv_ddr_misl_phy_drv_ctrl_p_get()
2860 unsigned int drv_ctrl_n = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_ctrl_n); in mv_ddr_misl_phy_drv_ctrl_n_get()
2875 odt_p = mv_ddr_misl_phy_odt_calc(tm->edata.phy_edata.odt_p[cs_num - 1]); in mv_ddr_misl_phy_odt_p_get()
2890 odt_n = mv_ddr_misl_phy_odt_calc(tm->edata.phy_edata.odt_n[cs_num - 1]); in mv_ddr_misl_phy_odt_n_get()