233 int ddr3_tip_tune_training_params(u32 dev_num,  in ddr3_tip_tune_training_params()
279 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable)  in ddr3_tip_configure_cs()
335 int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_prm)  in hws_ddr3_tip_init_controller()
676 static int ddr3_tip_rev2_rank_control(u32 dev_num, u32 if_id)  in ddr3_tip_rev2_rank_control()
730 static int ddr3_tip_rev3_rank_control(u32 dev_num, u32 if_id)  in ddr3_tip_rev3_rank_control()
763 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id)  in ddr3_tip_rank_control()
798 int ddr3_tip_validate_algo_components(u8 dev_num)  in ddr3_tip_validate_algo_components()
903 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type)  in hws_ddr3_tip_run_alg()
942 static int odt_test(u32 dev_num, enum hws_algo_type algo_type)  in odt_test()
982 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable)  in hws_ddr3_tip_select_ddr_controller()
991 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,  in ddr3_tip_if_write()
1002 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,  in ddr3_tip_if_read()
1013 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,  in ddr3_tip_if_polling()
1065 int ddr3_tip_bus_read(u32 dev_num, u32 if_id,  in ddr3_tip_bus_read()
1076 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access,  in ddr3_tip_bus_write()
1089 int ddr3_tip_bus_read_modify_write(u32 dev_num, enum hws_access_type access_type,  in ddr3_tip_bus_read_modify_write()
1123 int adll_calibration(u32 dev_num, enum hws_access_type access_type,  in adll_calibration()
1196 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,  in ddr3_tip_freq_set()
1586 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,  in ddr3_tip_write_odt()
1619 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,  in ddr3_tip_set_timing()
1764 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset)  in ddr3_tip_write_cs_result()
1804 int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask)  in ddr3_tip_write_mrs_cmd()
1835 int ddr3_tip_reset_fifo_ptr(u32 dev_num)  in ddr3_tip_reset_fifo_ptr()
1874 int ddr3_tip_ddr3_reset_phy_regs(u32 dev_num)  in ddr3_tip_ddr3_reset_phy_regs()
1946 int ddr3_tip_restore_dunit_regs(u32 dev_num)  in ddr3_tip_restore_dunit_regs()
1976 int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2)  in ddr3_tip_adll_regs_bypass()
2003 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)  in ddr3_tip_ddr3_training_main_flow()
2471 static int ddr3_tip_ddr3_auto_tune(u32 dev_num)  in ddr3_tip_ddr3_auto_tune()
2540 int ddr3_tip_enable_init_sequence(u32 dev_num)  in ddr3_tip_enable_init_sequence()
2586 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table)  in ddr3_tip_register_dq_table()