Lines Matching refs:MAX_INTERFACE_NUM
90 u32 ctrl_sweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM];
91 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
92 u32 ctrl_adll1[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
93 u32 ctrl_level_phase[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
114 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_reg_dump()
121 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()
135 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()
376 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_log()
515 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_print_stability_log()
520 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_print_stability_log()
539 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_print_stability_log()
672 int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], in ddr3_tip_read_adll_value()
684 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_read_adll_value()
706 int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], in ddr3_tip_write_adll_value()
718 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_adll_value()
741 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], in read_phase_value()
750 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in read_phase_value()
769 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], in write_leveling_value()
770 u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr) in write_leveling_value()
778 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in write_leveling_value()
808 u32 ctrl_sweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM];
809 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
838 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_adll()
869 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]) in print_adll()
877 for (i = 0; i < MAX_INTERFACE_NUM; i++) in print_adll()
885 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]) in print_ph()
893 for (i = 0; i < MAX_INTERFACE_NUM; i++) in print_ph()
922 for (i_id = 0; i_id <= MAX_INTERFACE_NUM - 1; i_id++) { in ddr3_tip_compare()
928 for (i_id = 0; i_id <= MAX_INTERFACE_NUM - 1; i_id++) { in ddr3_tip_compare()
948 u32 res[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_run_sweep_test()
975 if_id <= MAX_INTERFACE_NUM - 1; in ddr3_tip_run_sweep_test()
987 for (adll = 0; adll < (MAX_INTERFACE_NUM * MAX_BUS_NUM); adll++) in ddr3_tip_run_sweep_test()
1013 if_id < MAX_INTERFACE_NUM; in ddr3_tip_run_sweep_test()
1042 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_run_sweep_test()
1061 if_id <= MAX_INTERFACE_NUM - 1; in ddr3_tip_run_sweep_test()
1094 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_run_leveling_sweep_test()
1095 u32 res[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_run_leveling_sweep_test()
1118 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_run_leveling_sweep_test()
1125 for (adll = 0; adll < MAX_INTERFACE_NUM * MAX_BUS_NUM; adll++) { in ddr3_tip_run_leveling_sweep_test()
1146 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_run_leveling_sweep_test()
1190 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_run_leveling_sweep_test()
1220 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_run_leveling_sweep_test()
1242 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_run_leveling_sweep_test()
1259 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_run_leveling_sweep_test()
1294 for (ui = 0; ui < MAX_INTERFACE_NUM; ui++) { in print_topology()
1344 u32 data_read[MAX_INTERFACE_NUM]; in run_xsb_test()
1347 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in run_xsb_test()