18 	int i = 0;  in lpddr4_cfg_umctl2()
20 	for (i = 0; i < num; i++) {  in lpddr4_cfg_umctl2()
33 		reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);  in ddr_init()
34 		reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);  in ddr_init()
35 		reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);  in ddr_init()
37 		reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F);  in ddr_init()
38 		reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);  in ddr_init()
53 	reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */  in ddr_init()
54 	reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */  in ddr_init()
60 	 * release [0]ddr1_preset_n, [1]ddr1_core_reset_n,  in ddr_init()
63 	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);  in ddr_init()
73 	 * RESET: <aresetn> for Port 0  DEASSERT(0)ED  in ddr_init()
75 	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);  in ddr_init()
76 	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);  in ddr_init()
78 	reg32_write(DDRC_DBG1(0), 0x00000000);  in ddr_init()
80 	/* [0]dis_auto_refresh=1 */  in ddr_init()
81 	reg32_write(DDRC_RFSHCTL3(0), 0x00000011);  in ddr_init()
84 	reg32_write(DDRC_PWRCTL(0), 0x000000a8);  in ddr_init()
87 		tmp = reg32_read(DDRC_STAT(0));  in ddr_init()
88 	} while ((tmp & 0x33f) != 0x223);  in ddr_init()
90 	reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */  in ddr_init()
93 	reg32_write(DDRC_SWCTL(0), 0x00000000);  in ddr_init()
96 	tmp = reg32_read(DDRC_MSTR2(0));  in ddr_init()
97 	if (tmp == 0x2)  in ddr_init()
98 		reg32_write(DDRC_DFIMISC(0), 0x00000210);  in ddr_init()
99 	else if (tmp == 0x1)  in ddr_init()
100 		reg32_write(DDRC_DFIMISC(0), 0x00000110);  in ddr_init()
102 		reg32_write(DDRC_DFIMISC(0), 0x00000010);  in ddr_init()
104 	/* step7 [0]--1: disable quasi-dynamic programming */  in ddr_init()
105 	reg32_write(DDRC_SWCTL(0), 0x00000001);  in ddr_init()
113 	 * step14 CalBusy.0 =1, indicates the calibrator is actively  in ddr_init()
117 		tmp = reg32_read(DDRPHY_CalBusy(0));  in ddr_init()
118 	} while ((tmp & 0x1));  in ddr_init()
122 	/* step15 [0]--0: to enable quasi-dynamic programming */  in ddr_init()
123 	reg32_write(DDRC_SWCTL(0), 0x00000000);  in ddr_init()
126 	tmp = reg32_read(DDRC_MSTR2(0));  in ddr_init()
127 	if (tmp == 0x2)  in ddr_init()
128 		reg32_write(DDRC_DFIMISC(0), 0x00000230);  in ddr_init()
129 	else if (tmp == 0x1)  in ddr_init()
130 		reg32_write(DDRC_DFIMISC(0), 0x00000130);  in ddr_init()
132 		reg32_write(DDRC_DFIMISC(0), 0x00000030);  in ddr_init()
134 	/* step17 [0]--1: disable quasi-dynamic programming */  in ddr_init()
135 	reg32_write(DDRC_SWCTL(0), 0x00000001);  in ddr_init()
138 		tmp = reg32_read(DDRC_DFISTAT(0));  in ddr_init()
139 	} while ((tmp & 0x1) == 0x0);  in ddr_init()
142 	reg32_write(DDRC_SWCTL(0), 0x00000000);  in ddr_init()
145 	tmp = reg32_read(DDRC_MSTR2(0));  in ddr_init()
146 	if (tmp == 0x2) {  in ddr_init()
147 		reg32_write(DDRC_DFIMISC(0), 0x00000210);  in ddr_init()
149 		reg32_write(DDRC_DFIMISC(0), 0x00000211);  in ddr_init()
150 	} else if (tmp == 0x1) {  in ddr_init()
151 		reg32_write(DDRC_DFIMISC(0), 0x00000110);  in ddr_init()
153 		reg32_write(DDRC_DFIMISC(0), 0x00000111);  in ddr_init()
156 		reg32_write(DDRC_DFIMISC(0), 0x00000010);  in ddr_init()
158 		reg32_write(DDRC_DFIMISC(0), 0x00000011);  in ddr_init()
161 	/* step23 [5]selfref_sw=0; */  in ddr_init()
162 	reg32_write(DDRC_PWRCTL(0), 0x00000008);  in ddr_init()
164 	reg32_write(DDRC_SWCTL(0), 0x00000001);  in ddr_init()
168 		tmp = reg32_read(DDRC_SWSTAT(0));  in ddr_init()
169 	} while ((tmp & 0x1) == 0x0);  in ddr_init()
172 	reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001);  in ddr_init()
174 	/* wait STAT.operating_mode([1:0] for ddr3) to normal state */  in ddr_init()
176 		tmp = reg32_read(DDRC_STAT(0));  in ddr_init()
177 	} while ((tmp & 0x3) != 0x1);  in ddr_init()
180 	reg32_write(DDRC_RFSHCTL3(0), 0x00000010);  in ddr_init()
182 	/* enable port 0 */  in ddr_init()
183 	reg32_write(DDRC_PCTRL_0(0), 0x00000001);  in ddr_init()