22 #define IMEM_OFFSET_ADDR 0x00050000
23 #define DMEM_OFFSET_ADDR 0x00054000
24 #define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
30 	u32 error = 0;  in ddr_load_train_firmware()
32 	unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;  in ddr_load_train_firmware()
38 	for (i = 0x0; i < IMEM_LEN; ) {  in ddr_load_train_firmware()
40 		writew(tmp32 & 0x0000ffff, pr_to32);  in ddr_load_train_firmware()
42 		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);  in ddr_load_train_firmware()
50 	for (i = 0x0; i < DMEM_LEN; ) {  in ddr_load_train_firmware()
52 		writew(tmp32 & 0x0000ffff, pr_to32);  in ddr_load_train_firmware()
54 		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);  in ddr_load_train_firmware()
63 	for (i = 0x0; i < IMEM_LEN; ) {  in ddr_load_train_firmware()
64 		tmp32 = (readw(pr_to32) & 0x0000ffff);  in ddr_load_train_firmware()
66 		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);  in ddr_load_train_firmware()
84 	for (i = 0x0; i < DMEM_LEN;) {  in ddr_load_train_firmware()
85 		tmp32 = (readw(pr_to32) & 0x0000ffff);  in ddr_load_train_firmware()
87 		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);  in ddr_load_train_firmware()
106 	int i = 0;  in ddrphy_trained_csr_save()
109 	dwc_ddrphy_apb_wr(0xd0000, 0x0);  in ddrphy_trained_csr_save()
110 	dwc_ddrphy_apb_wr(0xc0080, 0x3);  in ddrphy_trained_csr_save()
111 	for (i = 0; i < num; i++) {  in ddrphy_trained_csr_save()
116 	dwc_ddrphy_apb_wr(0xc0080, 0x2);  in ddrphy_trained_csr_save()
117 	dwc_ddrphy_apb_wr(0xd0000, 0x1);  in ddrphy_trained_csr_save()
123 	int i = 0;  in dram_config_save()
133 	for (i = 0; i < 4; i++)  in dram_config_save()
141 	for (i = 0; i < timing_info->ddrc_cfg_num; i++) {  in dram_config_save()
149 	for (i = 0; i < timing_info->ddrphy_cfg_num; i++) {  in dram_config_save()
157 	for (i = 0; i < ddrphy_trained_csr_num; i++) {  in dram_config_save()
165 	for (i = 0; i < timing_info->ddrphy_pie_num; i++) {  in dram_config_save()