Lines Matching +full:- +full:- +full:disable +full:- +full:pie
1 // SPDX-License-Identifier: GPL-2.0+
112 ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg); in ddrphy_trained_csr_save()
115 /* disable the ddrphy apb */ in ddrphy_trained_csr_save()
127 saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num; in dram_config_save()
128 saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num; in dram_config_save()
129 saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num; in dram_config_save()
130 saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num; in dram_config_save()
134 saved_timing->fsp_table[i] = timing_info->fsp_table[i]; in dram_config_save()
140 saved_timing->ddrc_cfg = cfg; in dram_config_save()
141 for (i = 0; i < timing_info->ddrc_cfg_num; i++) { in dram_config_save()
142 cfg->reg = timing_info->ddrc_cfg[i].reg; in dram_config_save()
143 cfg->val = timing_info->ddrc_cfg[i].val; in dram_config_save()
148 saved_timing->ddrphy_cfg = cfg; in dram_config_save()
149 for (i = 0; i < timing_info->ddrphy_cfg_num; i++) { in dram_config_save()
150 cfg->reg = timing_info->ddrphy_cfg[i].reg; in dram_config_save()
151 cfg->val = timing_info->ddrphy_cfg[i].val; in dram_config_save()
156 saved_timing->ddrphy_trained_csr = cfg; in dram_config_save()
158 cfg->reg = ddrphy_trained_csr[i].reg; in dram_config_save()
159 cfg->val = ddrphy_trained_csr[i].val; in dram_config_save()
163 /* save the ddrphy pie */ in dram_config_save()
164 saved_timing->ddrphy_pie = cfg; in dram_config_save()
165 for (i = 0; i < timing_info->ddrphy_pie_num; i++) { in dram_config_save()
166 cfg->reg = timing_info->ddrphy_pie[i].reg; in dram_config_save()
167 cfg->val = timing_info->ddrphy_pie[i].val; in dram_config_save()