Lines Matching refs:sdram_cfg_2
152 out_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
163 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
207 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); in fsl_ddr_set_memctl_regs()
332 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
364 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
366 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
386 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); in fsl_ddr_set_memctl_regs()
432 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
450 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); in fsl_ddr_set_memctl_regs()
452 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
484 setbits_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
486 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
502 setbits_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
504 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
509 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
550 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); in fsl_ddr_set_memctl_regs()