Lines Matching full:cl
141 debug("CL = %u ok on DIMM %u at tCK=%u ps with tCKmin_X_ps of %u\n", in compute_cas_latency()
154 debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_1_ps of %u\n", in compute_cas_latency()
167 debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_2_ps of %u\n", in compute_cas_latency()
482 * I. Because you are using CL=3 and need to do ODT on writes and in compute_lowest_common_dimm_parameters()
487 * 2. If so, is your lowest supported CL going to be 3? in compute_lowest_common_dimm_parameters()
491 * RL = AL + CL in compute_lowest_common_dimm_parameters()
494 * WL = AL + CL - 1 in compute_lowest_common_dimm_parameters()
495 * AL + CL - 1 >= 3 in compute_lowest_common_dimm_parameters()
496 * AL + CL >= 4 in compute_lowest_common_dimm_parameters()
500 * RL = AL + CL in compute_lowest_common_dimm_parameters()
502 * Since CL aren't usually less than 2, AL=0 is a minimum, in compute_lowest_common_dimm_parameters()
549 * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled in compute_lowest_common_dimm_parameters()