456 			     const common_timing_params_t *common_dimm,  in set_timing_cfg_3()  argument
477 	ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;  in set_timing_cfg_3()
478 	ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;  in set_timing_cfg_3()
479 	ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;  in set_timing_cfg_3()
483 	ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;  in set_timing_cfg_3()
485 	ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;  in set_timing_cfg_3()
488 	ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +  in set_timing_cfg_3()
508 			     const common_timing_params_t *common_dimm,  in set_timing_cfg_1()  argument
541 	pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);  in set_timing_cfg_1()
542 	acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);  in set_timing_cfg_1()
543 	acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);  in set_timing_cfg_1()
578 	refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;  in set_timing_cfg_1()
579 	wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);  in set_timing_cfg_1()
580 	acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);  in set_timing_cfg_1()
587 	refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;  in set_timing_cfg_1()
588 	wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);  in set_timing_cfg_1()
589 	acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);  in set_timing_cfg_1()
590 	wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);  in set_timing_cfg_1()
636 			     const common_timing_params_t *common_dimm,  in set_timing_cfg_2()  argument
679 	rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);  in set_timing_cfg_2()
729 			      const common_timing_params_t *common_dimm)  in set_ddr_sdram_rcw()  argument
734 	if (common_dimm->all_dimms_registered &&  in set_ddr_sdram_rcw()
735 	    !common_dimm->all_dimms_unbuffered)	{  in set_ddr_sdram_rcw()
752 				common_dimm->rcw[0] << 28 | \  in set_ddr_sdram_rcw()
753 				common_dimm->rcw[1] << 24 | \  in set_ddr_sdram_rcw()
754 				common_dimm->rcw[2] << 20 | \  in set_ddr_sdram_rcw()
755 				common_dimm->rcw[3] << 16 | \  in set_ddr_sdram_rcw()
756 				common_dimm->rcw[4] << 12 | \  in set_ddr_sdram_rcw()
757 				common_dimm->rcw[5] << 8 | \  in set_ddr_sdram_rcw()
758 				common_dimm->rcw[6] << 4 | \  in set_ddr_sdram_rcw()
759 				common_dimm->rcw[7];  in set_ddr_sdram_rcw()
761 				common_dimm->rcw[8] << 28 | \  in set_ddr_sdram_rcw()
762 				common_dimm->rcw[9] << 24 | \  in set_ddr_sdram_rcw()
764 				common_dimm->rcw[11] << 16 | \  in set_ddr_sdram_rcw()
765 				common_dimm->rcw[12] << 12 | \  in set_ddr_sdram_rcw()
766 				common_dimm->rcw[13] << 8 | \  in set_ddr_sdram_rcw()
767 				common_dimm->rcw[14] << 4 | \  in set_ddr_sdram_rcw()
784 			       const common_timing_params_t *common_dimm)  in set_ddr_sdram_cfg()  argument
807 	if (common_dimm->all_dimms_ecc_capable) {  in set_ddr_sdram_cfg()
814 	if (common_dimm->all_dimms_registered &&  in set_ddr_sdram_cfg()
815 	    !common_dimm->all_dimms_unbuffered)	{  in set_ddr_sdram_cfg()
977 				const common_timing_params_t *common_dimm,  in set_ddr_sdram_mode_2()  argument
996 	if (common_dimm->extended_op_srt)  in set_ddr_sdram_mode_2()
997 		srt = common_dimm->extended_op_srt;  in set_ddr_sdram_mode_2()
1065 				const common_timing_params_t *common_dimm,  in set_ddr_sdram_mode_2()  argument
1082 	if (common_dimm->extended_op_srt)  in set_ddr_sdram_mode_2()
1083 		srt = common_dimm->extended_op_srt;  in set_ddr_sdram_mode_2()
1141 				const common_timing_params_t *common_dimm,  in set_ddr_sdram_mode_2()  argument
1159 				const common_timing_params_t *common_dimm,  in set_ddr_sdram_mode_9()  argument
1272 				const common_timing_params_t *common_dimm,  in set_ddr_sdram_mode_10()  argument
1278 	unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);  in set_ddr_sdram_mode_10()
1328 				const common_timing_params_t *common_dimm)  in set_ddr_sdram_interval()  argument
1333 	refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);  in set_ddr_sdram_interval()
1350 			       const common_timing_params_t *common_dimm,  in set_ddr_sdram_mode()  argument
1423 	wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);  in set_ddr_sdram_mode()
1521 			       const common_timing_params_t *common_dimm,  in set_ddr_sdram_mode()  argument
1598 	wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);  in set_ddr_sdram_mode()
1717 			       const common_timing_params_t *common_dimm,  in set_ddr_sdram_mode()  argument
1787 	wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);  in set_ddr_sdram_mode()
1998 			     const common_timing_params_t *common_dimm)  in set_timing_cfg_7()  argument
2004 	txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));  in set_timing_cfg_7()
2049 			     const common_timing_params_t *common_dimm,  in set_timing_cfg_8()  argument
2054 	int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);  in set_timing_cfg_8()
2078 	acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);  in set_timing_cfg_8()
2101 			     const common_timing_params_t *common_dimm)  in set_timing_cfg_9()  argument
2108 			picos_to_mclk(ctrl_num, common_dimm->trfc_slr_ps);  in set_timing_cfg_9()
2350 			       const common_timing_params_t *common_dimm,  in compute_fsl_memctl_config_regs()  argument
2399 	if (common_dimm == NULL) {  in compute_fsl_memctl_config_regs()
2411 		: common_dimm->lowest_common_spd_caslat;  in compute_fsl_memctl_config_regs()
2415 		: common_dimm->additive_latency;  in compute_fsl_memctl_config_regs()
2455 			sa = common_dimm->base_address;  in compute_fsl_memctl_config_regs()
2456 			ea = sa + common_dimm->total_mem - 1;  in compute_fsl_memctl_config_regs()
2469 				sa = common_dimm->base_address;  in compute_fsl_memctl_config_regs()
2470 				ea = sa + common_dimm->total_mem - 1;  in compute_fsl_memctl_config_regs()
2555 	set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,  in compute_fsl_memctl_config_regs()
2557 	set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);  in compute_fsl_memctl_config_regs()
2558 	set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,  in compute_fsl_memctl_config_regs()
2563 	set_ddr_sdram_cfg(ddr, popts, common_dimm);  in compute_fsl_memctl_config_regs()
2572 	set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,  in compute_fsl_memctl_config_regs()
2574 	set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);  in compute_fsl_memctl_config_regs()
2576 	set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);  in compute_fsl_memctl_config_regs()
2577 	set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);  in compute_fsl_memctl_config_regs()
2579 	set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm);  in compute_fsl_memctl_config_regs()
2581 	set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);  in compute_fsl_memctl_config_regs()
2591 	set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm);  in compute_fsl_memctl_config_regs()
2592 	set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);  in compute_fsl_memctl_config_regs()
2593 	set_timing_cfg_9(ctrl_num, ddr, popts, common_dimm);  in compute_fsl_memctl_config_regs()