143 	param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1;  in phy_mgr_initialize()
312 	scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,  in scc_mgr_set_dqs_io_in_delay()
319 		    rwcfg->mem_dq_per_write_dqs + 1 + dm,  in scc_mgr_set_dm_in_delay()
330 	scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,  in scc_mgr_set_dqs_out1_delay()
337 		    rwcfg->mem_dq_per_write_dqs + 1 + dm,  in scc_mgr_set_dm_out1_delay()
583 		for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {  in scc_mgr_zero_group()
643 	for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {  in scc_mgr_apply_group_dq_out1_delay()
685 	for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++)  in scc_mgr_apply_group_all_out_delay_add()
1178 	const u32 shift_ratio = rwcfg->mem_dq_per_write_dqs /  in rw_mgr_mem_calibrate_write_test()
1985 	const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :  in search_stop_check()
2040 	const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :  in search_left_edge()
2151 	const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :  in search_right_edge()
2178 				for (i = 0; i < rwcfg->mem_dq_per_write_dqs;  in search_right_edge()
2269 	const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :  in get_window_mid_index()
2320 	const s32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :  in center_dq_windows()
2953 	int left_edge[rwcfg->mem_dq_per_write_dqs];  in rw_mgr_mem_calibrate_writes_center()
2954 	int right_edge[rwcfg->mem_dq_per_write_dqs];  in rw_mgr_mem_calibrate_writes_center()
2973 			  (rwcfg->mem_dq_per_write_dqs << 2));  in rw_mgr_mem_calibrate_writes_center()
2982 	for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {  in rw_mgr_mem_calibrate_writes_center()
3365 			write_test_bgn += rwcfg->mem_dq_per_write_dqs) {  in mem_calibrate()
3749 		   rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs,  in sdram_calibration_full()