Lines Matching full:dq
353 /* load up dq config settings */
469 * bits: 1:1 = 1'b1 - DQ bypass in scc_mgr_set_hhp_extras()
534 /* Multicast to all DQ enables. */ in scc_set_bypass_mode()
574 * Zero DQ, DM, DQS and OCT configs for a group.
582 /* Zero all DQ config settings. */ in scc_mgr_zero_group()
589 /* Multicast to all DQ enables. */ in scc_mgr_zero_group()
620 * apply and load a particular input delay for the DQ pins in a group
621 * group_bgn is the index of the first dq pin (in the write group)
634 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
637 * Apply and load a particular output delay for the DQ pins in a group.
673 …* scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, …
677 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
684 /* DQ shift */ in scc_mgr_apply_group_all_out_delay_add()
726 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
2018 * search_left_edge() - Find left edge of DQ/DQS working phase
2025 * @left_edge: Left edge of the DQ/DQS phase
2026 * @right_edge: Right edge of the DQ/DQS phase
2029 * Find left edge of DQ/DQS working phase.
2081 /* Reset DQ delay chains to 0 */ in search_left_edge()
2127 * search_right_edge() - Find right edge of DQ/DQS working phase
2135 * @left_edge: Left edge of the DQ/DQS phase
2136 * @right_edge: Right edge of the DQ/DQS phase
2139 * Find right edge of DQ/DQS working phase.
2258 * get_window_mid_index() - Find the best middle setting of DQ/DQS phase
2260 * @left_edge: Left edge of the DQ/DQS phase
2261 * @right_edge: Right edge of the DQ/DQS phase
2262 * @mid_min: Best DQ/DQS phase middle setting
2264 * Find index and value of the middle of the DQ/DQS working phase.
2273 /* Find middle of window for each DQ bit */ in get_window_mid_index()
2300 * center_dq_windows() - Center the DQ/DQS windows
2302 * @left_edge: Left edge of the DQ/DQS phase
2303 * @right_edge: Right edge of the DQ/DQS phase
2304 * @mid_min: Adjusted DQ/DQS phase middle setting
2305 * @orig_mid_min: Original DQ/DQS phase middle setting
2306 * @min_index: DQ/DQS phase middle setting index
2308 * @dq_margin: Amount of shift for the DQ
2311 * Align the DQ/DQS windows in each group.
2333 /* add delay to bring centre of all DQ windows to the same "level" */ in center_dq_windows()
2379 * rw_mgr_mem_calibrate_vfifo_center() - Per-bit deskew DQ and centering
2386 * Per-bit deskew DQ and centering.
2492 /* Add delay to bring centre of all DQ windows to the same "level". */ in rw_mgr_mem_calibrate_vfifo_center()
2525 * @phase: DQ/DQS phase
2536 /* Set a particular DQ/DQS phase. */ in rw_mgr_mem_calibrate_guaranteed_write()
2569 * DQS enable calibration ensures reliable capture of the DQ signal without
2580 /* We start at zero, so have one less dq to devide among */ in rw_mgr_mem_calibrate_dqs_enable_calibration()
2588 /* Try different dq_in_delays since the DQ path is shorter than DQS. */ in rw_mgr_mem_calibrate_dqs_enable_calibration()
2625 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2631 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2679 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2680 * - we also do a per-bit deskew on the DQ lines.
2729 /* 3) Centering DQ/DQS */ in rw_mgr_mem_calibrate_vfifo()
2764 * rw_mgr_mem_calibrate_vfifo_end() - DQ/DQS Centering.
2768 * Stage 3: DQ/DQS Centering.
2887 * ourselves to width of DQ unnecessarily. in search_window()
3013 /* Add delay to bring centre of all DQ windows to the same "level". */ in rw_mgr_mem_calibrate_writes_center()
3067 /* Only move right, since we are not moving DQS/DQ. */ in rw_mgr_mem_calibrate_writes_center()
3330 /* Only needed once to set all groups, pins, DQ, DQS, DM. */ in mem_calibrate()
3747 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ", in sdram_calibration_full()
3753 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ", in sdram_calibration_full()