ddr/altera/sdram_s10.c

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
19 static const struct socfpga_system_manager *sysmgr_regs =
50 static u32 hmc_readl(u32 reg)  in hmc_readl()
55 static u32 hmc_ecc_readl(u32 reg)  in hmc_ecc_readl()
60 static u32 hmc_ecc_writel(u32 data, u32 reg)  in hmc_ecc_writel()
65 static u32 ddr_sch_writel(u32 data, u32 reg)  in ddr_sch_writel()
82 static int emif_clear(void)  in emif_clear()
92 static int emif_reset(void)  in emif_reset()
105 		return -1;  in emif_reset()
131 static int poll_hmc_clock_status(void)  in poll_hmc_clock_status()
133 	return wait_for_bit_le32(&sysmgr_regs->hmc_clk,  in poll_hmc_clock_status()
138  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
195 		return -1;  in sdram_mmr_init_full()
215 		return -1;  in sdram_mmr_init_full()
234 	 *	bit[8]   = 1 if user-mode OCT is present  in sdram_mmr_init_full()
238 	 *	bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,  in sdram_mmr_init_full()
239 	 *			    3=EAP, 4-6 are reserved)  in sdram_mmr_init_full()
267 	 *  RDTOMISS = tRTP + tRP + tRCD - BL/2  in sdram_mmr_init_full()
269 	 *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...  in sdram_mmr_init_full()
272 	 *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD  in sdram_mmr_init_full()
278 		       CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -  in sdram_mmr_init_full()
281 		       (burst_len >> 1)) >> 1) -  in sdram_mmr_init_full()
338 		gd->ram_size = PHYS_SDRAM_1_SIZE;  in sdram_mmr_init_full()
340 		gd->ram_size = size;  in sdram_mmr_init_full()
369  * sdram_calculate_size() - Calculate SDRAM size