Lines Matching full:gate
16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_SPI2] = GATE(0x060, BIT(22)),
23 [CLK_BUS_SPI3] = GATE(0x060, BIT(23)),
24 [CLK_BUS_OTG] = GATE(0x060, BIT(25)),
25 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
26 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
27 [CLK_BUS_EHCI2] = GATE(0x060, BIT(28)),
28 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
29 [CLK_BUS_OHCI1] = GATE(0x060, BIT(30)),
30 [CLK_BUS_OHCI2] = GATE(0x060, BIT(31)),
32 [CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
34 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
35 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
36 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
37 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
38 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
39 [CLK_BUS_UART5] = GATE(0x06c, BIT(21)),
40 [CLK_BUS_UART6] = GATE(0x06c, BIT(22)),
41 [CLK_BUS_UART7] = GATE(0x06c, BIT(23)),
43 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
44 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
45 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
46 [CLK_SPI3] = GATE(0x0ac, BIT(31)),
48 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
49 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
50 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
51 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
52 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
53 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),