Lines Matching +full:0 +full:x430
16 [CLK_SPI0] = GATE(0x430, BIT(31)),
17 [CLK_SPI1] = GATE(0x434, BIT(31)),
18 [CLK_SPI2] = GATE(0x438, BIT(31)),
19 [CLK_SPI3] = GATE(0x43c, BIT(31)),
21 [CLK_BUS_MMC] = GATE(0x580, BIT(8)),
22 [CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
23 [CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
24 [CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
25 [CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
27 [CLK_BUS_UART0] = GATE(0x594, BIT(16)),
28 [CLK_BUS_UART1] = GATE(0x594, BIT(17)),
29 [CLK_BUS_UART2] = GATE(0x594, BIT(18)),
30 [CLK_BUS_UART3] = GATE(0x594, BIT(19)),
31 [CLK_BUS_UART4] = GATE(0x594, BIT(20)),
32 [CLK_BUS_UART5] = GATE(0x594, BIT(21)),
36 [RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
37 [RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
38 [RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
39 [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
40 [RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
42 [RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
43 [RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
44 [RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
45 [RST_BUS_UART3] = RESET(0x5b4, BIT(19)),
46 [RST_BUS_UART4] = RESET(0x5b4, BIT(20)),
47 [RST_BUS_UART5] = RESET(0x5b4, BIT(21)),
51 [0] = GATE(0x0, BIT(16)),
52 [1] = GATE(0x4, BIT(16)),
53 [2] = GATE(0x8, BIT(16)),
54 [3] = GATE(0xc, BIT(16)),
58 [0] = GATE(0x0, BIT(18)),
59 [1] = GATE(0x4, BIT(18)),
60 [2] = GATE(0x8, BIT(18)),
61 [3] = GATE(0xc, BIT(18)),