Lines Matching full:gate
16 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
20 [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
21 [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
23 [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)),
24 [CLK_AHB1_SPI3] = GATE(0x060, BIT(23)),
25 [CLK_AHB1_OTG] = GATE(0x060, BIT(24)),
26 [CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)),
27 [CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)),
28 [CLK_AHB1_OHCI0] = GATE(0x060, BIT(29)),
29 [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
30 [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
32 [CLK_APB2_UART0] = GATE(0x06c, BIT(16)),
33 [CLK_APB2_UART1] = GATE(0x06c, BIT(17)),
34 [CLK_APB2_UART2] = GATE(0x06c, BIT(18)),
35 [CLK_APB2_UART3] = GATE(0x06c, BIT(19)),
36 [CLK_APB2_UART4] = GATE(0x06c, BIT(20)),
37 [CLK_APB2_UART5] = GATE(0x06c, BIT(21)),
39 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
40 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
41 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
42 [CLK_SPI3] = GATE(0x0ac, BIT(31)),
44 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
45 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
46 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
47 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
48 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
49 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),