19  * the CLN28HPC variant of the Analog Bits Wide Range PLL.  The
30  * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
82  * Select the value to be presented to the PLL RANGE input signals, based
85  * range selection.
87  * Return: The RANGE value to be presented to the PLL configuration inputs,
92 	u8 range;  in __wrpll_calc_filter_range()  local
96 		WARN(1, "%s: post-divider reference freq out of range: %lu",  in __wrpll_calc_filter_range()
102 		range = 1;  in __wrpll_calc_filter_range()
104 		range = 2;  in __wrpll_calc_filter_range()
106 		range = 3;  in __wrpll_calc_filter_range()
108 		range = 4;  in __wrpll_calc_filter_range()
110 		range = 5;  in __wrpll_calc_filter_range()
112 		range = 6;  in __wrpll_calc_filter_range()
114 		range = 7;  in __wrpll_calc_filter_range()
116 	return range;  in __wrpll_calc_filter_range()
193  * Returns: 0 upon success or -1 if the reference clock rate is out of range.
272 			pr_err("%s: PLL input rate is out of range\n",  in analogbits_wrpll_configure_for_rate()
315 		/* Ensure rounding didn't take us out of range */  in analogbits_wrpll_configure_for_rate()
338 	c->range = __wrpll_calc_filter_range(post_divr_freq);  in analogbits_wrpll_configure_for_rate()