1 // SPDX-License-Identifier: GPL-2.0
18  * The FU540 PRCI implements clock and reset control for the SiFive
19  * FU540-C000 chip.   This driver assumes that it has sole control
25  * https://github.com/riscv/riscv-linux
28  * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
32 #include <clk-uclass.h>
40 #include <dt-bindings/clk/sifive-fu540-prci.h>
42 #include "analogbits-wrpll-cln28hpc.h"
155  * struct __prci_data - per-device-instance data
159  * PRCI per-device instance data
167  * struct __prci_wrpll_data - WRPLL configuration and integration data
198  * struct __prci_clock - describes a clock device managed by PRCI
199  * @name: user-readable clock name string - should match the manual
202  * @hw: Linux-private clock data
203  * @pwd: WRPLL-specific data, associated with this clock (if not NULL)
204  * @pd: PRCI-specific data associated with this clock (if not NULL)
206  * PRCI clock data.  Used by the PRCI driver to register PRCI-provided
222  * __prci_readl() - read from a PRCI register
236 	return readl(pd->base + offs);  in __prci_readl()
241 	return writel(v, pd->base + offs);  in __prci_writel()
244 /* WRPLL-related private functions */
247  * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
251  * Given a value @r read from an FU540 PRCI PLL configuration register,
266 	c->divr = v;  in __prci_wrpll_unpack()
270 	c->divf = v;  in __prci_wrpll_unpack()
274 	c->divq = v;  in __prci_wrpll_unpack()
278 	c->range = v;  in __prci_wrpll_unpack()
280 	c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |  in __prci_wrpll_unpack()
284 		c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;  in __prci_wrpll_unpack()
286 		c->flags |= WRPLL_FLAGS_EXT_FEEDBACK_MASK;  in __prci_wrpll_unpack()
290  * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
308 	r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;  in __prci_wrpll_pack()
309 	r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;  in __prci_wrpll_pack()
310 	r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;  in __prci_wrpll_pack()
311 	r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;  in __prci_wrpll_pack()
312 	if (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK)  in __prci_wrpll_pack()
319  * __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI
333 	__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));  in __prci_wrpll_read_cfg()
337  * __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI
354 	__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);  in __prci_wrpll_write_cfg()
356 	memcpy(&pwd->c, c, sizeof(struct analogbits_wrpll_cfg));  in __prci_wrpll_write_cfg()
362  * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
382  * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
405 	struct __prci_wrpll_data *pwd = pc->pwd;  in sifive_fu540_prci_wrpll_recalc_rate()
407 	return analogbits_wrpll_calc_output_rate(&pwd->c, parent_rate);  in sifive_fu540_prci_wrpll_recalc_rate()
415 	struct __prci_wrpll_data *pwd = pc->pwd;  in sifive_fu540_prci_wrpll_round_rate()
418 	memcpy(&c, &pwd->c, sizeof(c));  in sifive_fu540_prci_wrpll_round_rate()
429 	struct __prci_wrpll_data *pwd = pc->pwd;  in sifive_fu540_prci_wrpll_set_rate()
430 	struct __prci_data *pd = pc->pd;  in sifive_fu540_prci_wrpll_set_rate()
433 	r = analogbits_wrpll_configure_for_rate(&pwd->c, rate, parent_rate);  in sifive_fu540_prci_wrpll_set_rate()
435 		return -ERANGE;  in sifive_fu540_prci_wrpll_set_rate()
437 	if (pwd->bypass)  in sifive_fu540_prci_wrpll_set_rate()
438 		pwd->bypass(pd);  in sifive_fu540_prci_wrpll_set_rate()
440 	__prci_wrpll_write_cfg(pd, pwd, &pwd->c);  in sifive_fu540_prci_wrpll_set_rate()
442 	udelay(analogbits_wrpll_calc_max_lock_us(&pwd->c));  in sifive_fu540_prci_wrpll_set_rate()
444 	if (pwd->no_bypass)  in sifive_fu540_prci_wrpll_set_rate()
445 		pwd->no_bypass(pd);  in sifive_fu540_prci_wrpll_set_rate()
466 	struct __prci_data *pd = pc->pd;  in sifive_fu540_prci_tlclksel_recalc_rate()
533 	if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)  in sifive_fu540_prci_get_rate()
534 		return -ENXIO;  in sifive_fu540_prci_get_rate()
536 	pc = &__prci_init_clocks[clk->id];  in sifive_fu540_prci_get_rate()
537 	if (!pc->pd || !pc->ops->recalc_rate)  in sifive_fu540_prci_get_rate()
538 		return -ENXIO;  in sifive_fu540_prci_get_rate()
540 	return pc->ops->recalc_rate(pc, clk_get_rate(&pc->pd->parent));  in sifive_fu540_prci_get_rate()
548 	if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)  in sifive_fu540_prci_set_rate()
549 		return -ENXIO;  in sifive_fu540_prci_set_rate()
551 	pc = &__prci_init_clocks[clk->id];  in sifive_fu540_prci_set_rate()
552 	if (!pc->pd || !pc->ops->set_rate)  in sifive_fu540_prci_set_rate()
553 		return -ENXIO;  in sifive_fu540_prci_set_rate()
555 	err = pc->ops->set_rate(pc, rate, clk_get_rate(&pc->pd->parent));  in sifive_fu540_prci_set_rate()
568 	pd->base = (void *)dev_read_addr(dev);  in sifive_fu540_prci_probe()
569 	if (IS_ERR(pd->base))  in sifive_fu540_prci_probe()
570 		return PTR_ERR(pd->base);  in sifive_fu540_prci_probe()
572 	err = clk_get_by_index(dev, 0, &pd->parent);  in sifive_fu540_prci_probe()
578 		pc->pd = pd;  in sifive_fu540_prci_probe()
579 		if (pc->pwd)  in sifive_fu540_prci_probe()
580 			__prci_wrpll_read_cfg(pd, pc->pwd);  in sifive_fu540_prci_probe()
592 	{ .compatible = "sifive,fu540-c000-prci0" },
598 	.name = "sifive-fu540-prci",