85 	rk_clrsetreg(&pll->con3, WORK_MODE_MASK,  in rkclk_set_pll()
93 	rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT);  in rkclk_set_pll()
94 	rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK,  in rkclk_set_pll()
98 	rk_clrsetreg(&pll->con2, FRACDIV_MASK,  in rkclk_set_pll()
111 	rk_clrsetreg(&pll->con3, WORK_MODE_MASK,  in rkclk_set_pll()
160 		rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK,  in rv1108_mac_set_clk()
181 		rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK,  in rv1108_sfc_set_clk()
207 	rk_clrsetreg(&cru->clksel_con[22],  in rv1108_saradc_set_clk()
232 	rk_clrsetreg(&cru->clksel_con[28],  in rv1108_aclk_vio1_set_clk()
258 	rk_clrsetreg(&cru->clksel_con[28],  in rv1108_aclk_vio0_set_clk()
264 	rk_clrsetreg(&cru->clksel_con[29],  in rv1108_aclk_vio0_set_clk()
268 	rk_clrsetreg(&cru->clksel_con[29],  in rv1108_aclk_vio0_set_clk()
293 	rk_clrsetreg(&cru->clksel_con[32],  in rv1108_dclk_vop_set_clk()
323 	rk_clrsetreg(&cru->clksel_con[2],  in rv1108_aclk_bus_set_clk()
375 	rk_clrsetreg(&cru->clksel_con[23],  in rv1108_aclk_peri_set_clk()
391 	rk_clrsetreg(&cru->clksel_con[23],  in rv1108_hclk_peri_set_clk()
406 	rk_clrsetreg(&cru->clksel_con[23],  in rv1108_pclk_peri_set_clk()
456 		rk_clrsetreg(&cru->clksel_con[19],  in rv1108_i2c_set_clk()
462 		rk_clrsetreg(&cru->clksel_con[19],  in rv1108_i2c_set_clk()
468 		rk_clrsetreg(&cru->clksel_con[20],  in rv1108_i2c_set_clk()
474 		rk_clrsetreg(&cru->clksel_con[20],  in rv1108_i2c_set_clk()
515 		rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK,  in rv1108_mmc_set_clk()
520 		rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK,  in rv1108_mmc_set_clk()
526 	rk_clrsetreg(&cru->clksel_con[26], EMMC_CLK_DIV_MASK,  in rv1108_mmc_set_clk()
653 	rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK,  in rkclk_init()