50 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
549 	return DIV_TO_RATE(GPLL_HZ, div);  in rk3399_i2c_get_clk()
557 	src_clk_div = GPLL_HZ / hz;  in rk3399_i2c_set_clk()
648 	return DIV_TO_RATE(GPLL_HZ, div);  in rk3399_spi_get_clk()
656 	src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;  in rk3399_spi_set_clk()
746 		return DIV_TO_RATE(GPLL_HZ, div);  in rk3399_mmc_get_clk()
760 		src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);  in rk3399_mmc_set_clk()
779 		src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc);  in rk3399_mmc_set_clk()
788 		src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);  in rk3399_mmc_set_clk()
1117 	aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;  in rkclk_init()
1118 	assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);  in rkclk_init()
1137 	aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;  in rkclk_init()
1138 	assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);  in rkclk_init()
1157 	hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;  in rkclk_init()
1159 	       GPLL_HZ && (hclk_div < 0x1f));  in rkclk_init()