256 	rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift);  in rkclk_set_pll()
259 	rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK,  in rkclk_set_pll()
262 	rk_clrsetreg(&pll_con[0],  in rkclk_set_pll()
266 	rk_clrsetreg(&pll_con[1],  in rkclk_set_pll()
276 	rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift);  in rkclk_set_pll()
294 	rk_clrsetreg(&cru->clksel_con[28],  in rkclk_init()
298 	rk_clrsetreg(&cru->clksel_con[29],  in rkclk_init()
317 	rk_clrsetreg(&cru->clksel_con[0],  in rk3328_configure_cpu()
322 	rk_clrsetreg(&cru->clksel_con[1],  in rk3328_configure_cpu()
367 		rk_clrsetreg(&cru->clksel_con[34],  in rk3328_i2c_set_clk()
374 		rk_clrsetreg(&cru->clksel_con[34],  in rk3328_i2c_set_clk()
381 		rk_clrsetreg(&cru->clksel_con[35],  in rk3328_i2c_set_clk()
388 		rk_clrsetreg(&cru->clksel_con[35],  in rk3328_i2c_set_clk()
429 			rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK,  in rk3328_gmac2io_set_clk()
491 		rk_clrsetreg(&cru->clksel_con[con_id],  in rk3328_mmc_set_clk()
496 		rk_clrsetreg(&cru->clksel_con[con_id],  in rk3328_mmc_set_clk()
519 	rk_clrsetreg(&cru->clksel_con[24],  in rk3328_pwm_set_clk()
545 	rk_clrsetreg(&cru->clksel_con[23],  in rk3328_saradc_set_clk()