Lines Matching refs:GPLL_HZ
37 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
290 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; in rkclk_init()
355 return DIV_TO_RATE(GPLL_HZ, div); in rk3328_i2c_get_clk()
362 src_clk_div = GPLL_HZ / hz; in rk3328_i2c_set_clk()
399 return DIV_TO_RATE(GPLL_HZ, src_clk_div); in rk3328_i2c_set_clk()
423 pll_rate = GPLL_HZ; in rk3328_gmac2io_set_clk()
463 return DIV_TO_RATE(GPLL_HZ, div) / 2; in rk3328_mmc_get_clk()
486 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); in rk3328_mmc_set_clk()
512 return DIV_TO_RATE(GPLL_HZ, div); in rk3328_pwm_get_clk()
517 u32 div = GPLL_HZ / hz; in rk3328_pwm_set_clk()
524 return DIV_TO_RATE(GPLL_HZ, div); in rk3328_pwm_set_clk()